lvds_pll_cntl 58 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; lvds_pll_cntl 95 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl 96 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl |= RADEON_LVDS_PLL_EN; lvds_pll_cntl 97 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); lvds_pll_cntl 100 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl 101 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; lvds_pll_cntl 102 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); lvds_pll_cntl 191 drivers/gpu/drm/radeon/radeon_legacy_encoders.c uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; lvds_pll_cntl 195 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl 196 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; lvds_pll_cntl 225 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); lvds_pll_cntl 230 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; lvds_pll_cntl 235 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; lvds_pll_cntl 241 drivers/gpu/drm/radeon/radeon_legacy_encoders.c WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); lvds_pll_cntl 1343 drivers/video/fbdev/aty/radeon_base.c save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); lvds_pll_cntl 1910 drivers/video/fbdev/aty/radeon_base.c newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; lvds_pll_cntl 226 drivers/video/fbdev/aty/radeonfb.h u32 lvds_pll_cntl;