lvds_phy_cfg0 104 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c uint32_t lvds_intf = 0, lvds_phy_cfg0 = 0; lvds_phy_cfg0 224 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0; lvds_phy_cfg0 229 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c lvds_phy_cfg0 = MDP4_LVDS_PHY_CFG0_CHANNEL0 | lvds_phy_cfg0 244 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0); lvds_phy_cfg0 250 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c lvds_phy_cfg0 |= MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE; lvds_phy_cfg0 251 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, lvds_phy_cfg0);