lvds_intf         104 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t lvds_intf = 0, lvds_phy_cfg0 = 0;
lvds_intf         158 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 			lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN |
lvds_intf         167 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 			lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN |
lvds_intf         203 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 			lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN |
lvds_intf         210 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 			lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN |
lvds_intf         214 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 		lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT;
lvds_intf         225 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 		lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN |
lvds_intf         231 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 		lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN |
lvds_intf         240 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 		lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP;
lvds_intf         242 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	lvds_intf |= MDP4_LCDC_LVDS_INTF_CTL_ENABLE;
lvds_intf         245 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_INTF_CTL, lvds_intf);