lvds 2008 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c struct amdgpu_encoder_atom_dig *lvds = NULL; lvds 2015 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds = lvds 2018 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c if (!lvds) lvds 2021 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.clock = lvds 2023 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.hdisplay = lvds 2025 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.vdisplay = lvds 2027 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.htotal = lvds->native_mode.hdisplay + lvds 2029 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + lvds 2031 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + lvds 2033 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.vtotal = lvds->native_mode.vdisplay + lvds 2035 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + lvds 2037 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + lvds 2039 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->panel_pwr_delay = lvds 2041 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; lvds 2045 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; lvds 2047 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; lvds 2049 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; lvds 2051 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; lvds 2053 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; lvds 2055 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); lvds 2056 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); lvds 2059 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); lvds 2061 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->lcd_ss_id = lvds_info->info.ucSS_Id; lvds 2063 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c encoder->native_mode = lvds->native_mode; lvds 2066 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->linkb = true; lvds 2068 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->linkb = false; lvds 2121 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.width_mm = panel_res_record->usHSize; lvds 2122 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c lvds->native_mode.height_mm = panel_res_record->usVSize; lvds 2135 drivers/gpu/drm/amd/amdgpu/atombios_encoders.c return lvds; lvds 1212 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ATOM_LVDS_INFO_V12 *lvds; lvds 1220 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds = lvds 1223 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (!lvds) lvds 1226 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (1 != lvds->sHeader.ucTableFormatRevision lvds 1227 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c || 2 > lvds->sHeader.ucTableContentRevision) lvds 1234 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10; lvds 1237 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHActive); lvds 1243 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time); lvds 1246 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVActive); lvds 1252 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time); lvds 1254 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHSyncOffset); lvds 1256 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHSyncWidth); lvds 1258 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVSyncOffset); lvds 1260 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVSyncWidth); lvds 1261 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder; lvds 1262 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder; lvds 1264 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff; lvds 1267 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity; lvds 1270 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity; lvds 1272 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff; lvds 1274 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2; lvds 1276 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2; lvds 1278 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync; lvds 1280 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; lvds 1282 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock; lvds 1283 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->ss_id = lvds->ucSS_Id; lvds 1286 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate); lvds 1302 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c & lvds->ucLCDPanel_SpecialHandlingCap) lvds 1305 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_DUAL & lvds->ucLVDS_Misc) lvds 1308 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_888RGB & lvds->ucLVDS_Misc) lvds 1313 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT; lvds 1315 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_SPATIAL & lvds->ucLVDS_Misc) lvds 1318 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_TEMPORAL & lvds->ucLVDS_Misc) lvds 1321 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc) lvds 1331 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c ATOM_LCD_INFO_V13 *lvds; lvds 1339 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds = GET_IMAGE(ATOM_LCD_INFO_V13, DATA_TABLES(LCD_Info)); lvds 1341 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (!lvds) lvds 1344 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (!((1 == lvds->sHeader.ucTableFormatRevision) lvds 1345 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c && (3 <= lvds->sHeader.ucTableContentRevision))) lvds 1352 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10; lvds 1355 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHActive); lvds 1361 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time); lvds 1364 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVActive); lvds 1370 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time); lvds 1372 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHSyncOffset); lvds 1374 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usHSyncWidth); lvds 1376 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVSyncOffset); lvds 1378 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c le16_to_cpu(lvds->sLCDTiming.usVSyncWidth); lvds 1379 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder; lvds 1380 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder; lvds 1382 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff; lvds 1385 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity; lvds 1388 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity; lvds 1390 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff; lvds 1392 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2; lvds 1394 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2; lvds 1396 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync; lvds 1398 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; lvds 1400 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock; lvds 1401 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->ss_id = lvds->ucSS_Id; lvds 1405 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c & lvds->ucLCDPanel_SpecialHandlingCap) lvds 1411 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->sRefreshRateSupport.ucMinRefreshRateForDRR; lvds 1412 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate; lvds 1439 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_V13_DUAL & lvds->ucLCD_Misc) lvds 1442 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c if (ATOM_PANEL_MISC_V13_8BIT_PER_COLOR & lvds->ucLCD_Misc) lvds 1447 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT; lvds 847 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c struct lcd_info_v2_1 *lvds; lvds 855 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); lvds 857 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c if (!lvds) lvds 861 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c if (!((lvds->table_header.format_revision == 2) lvds 862 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c && (lvds->table_header.content_revision >= 1))) lvds 868 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; lvds 870 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); lvds 876 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); lvds 878 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); lvds 884 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); lvds 885 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); lvds 886 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); lvds 887 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); lvds 888 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); lvds 889 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; lvds 890 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; lvds 895 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo lvds 897 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo lvds 903 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo lvds 905 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo lvds 907 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo lvds 909 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); lvds 916 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); lvds 739 drivers/gpu/drm/gma500/cdv_intel_display.c u32 lvds = REG_READ(LVDS); lvds 741 drivers/gpu/drm/gma500/cdv_intel_display.c lvds |= lvds 749 drivers/gpu/drm/gma500/cdv_intel_display.c lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; lvds 751 drivers/gpu/drm/gma500/cdv_intel_display.c lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); lvds 758 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(LVDS, lvds); lvds 580 drivers/gpu/drm/gma500/cdv_intel_lvds.c u32 lvds; lvds 707 drivers/gpu/drm/gma500/cdv_intel_lvds.c lvds = REG_READ(LVDS); lvds 708 drivers/gpu/drm/gma500/cdv_intel_lvds.c pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; lvds 711 drivers/gpu/drm/gma500/cdv_intel_lvds.c if (crtc && (lvds & LVDS_PORT_EN)) { lvds 224 drivers/gpu/drm/gma500/psb_intel_display.c u32 lvds = REG_READ(LVDS); lvds 226 drivers/gpu/drm/gma500/psb_intel_display.c lvds &= ~LVDS_PIPEB_SELECT; lvds 228 drivers/gpu/drm/gma500/psb_intel_display.c lvds |= LVDS_PIPEB_SELECT; lvds 230 drivers/gpu/drm/gma500/psb_intel_display.c lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; lvds 235 drivers/gpu/drm/gma500/psb_intel_display.c lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); lvds 237 drivers/gpu/drm/gma500/psb_intel_display.c lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; lvds 244 drivers/gpu/drm/gma500/psb_intel_display.c REG_WRITE(LVDS, lvds); lvds 654 drivers/gpu/drm/gma500/psb_intel_lvds.c u32 lvds; lvds 772 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds = REG_READ(LVDS); lvds 773 drivers/gpu/drm/gma500/psb_intel_lvds.c pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; lvds 776 drivers/gpu/drm/gma500/psb_intel_lvds.c if (crtc && (lvds & LVDS_PORT_EN)) { lvds 11338 drivers/gpu/drm/i915/display/intel_display.c u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); lvds 11339 drivers/gpu/drm/i915/display/intel_display.c bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); lvds 11345 drivers/gpu/drm/i915/display/intel_display.c if (lvds & LVDS_CLKB_POWER_UP) lvds 824 drivers/gpu/drm/i915/display/intel_lvds.c u32 lvds; lvds 845 drivers/gpu/drm/i915/display/intel_lvds.c lvds = I915_READ(lvds_reg); lvds 848 drivers/gpu/drm/i915/display/intel_lvds.c if ((lvds & LVDS_DETECTED) == 0) lvds 854 drivers/gpu/drm/i915/display/intel_lvds.c if ((lvds & LVDS_PORT_EN) == 0) { lvds 924 drivers/gpu/drm/i915/display/intel_lvds.c lvds_encoder->init_lvds_val = lvds; lvds 993 drivers/gpu/drm/i915/display/intel_lvds.c lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; lvds 1463 drivers/gpu/drm/nouveau/dispnv50/disp.c struct nv50_disp_sor_lvds_script_v0 lvds; lvds 1464 drivers/gpu/drm/nouveau/dispnv50/disp.c } lvds = { lvds 1507 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0100; lvds 1509 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0200; lvds 1513 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0100; lvds 1516 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0100; lvds 1519 drivers/gpu/drm/nouveau/dispnv50/disp.c if (lvds.lvds.script & 0x0100) { lvds 1521 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0200; lvds 1524 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0200; lvds 1528 drivers/gpu/drm/nouveau/dispnv50/disp.c lvds.lvds.script |= 0x0200; lvds 1531 drivers/gpu/drm/nouveau/dispnv50/disp.c nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); lvds 1033 drivers/gpu/drm/nouveau/nouveau_bios.c parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); lvds 51 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds = to_panel_lvds(panel); lvds 53 drivers/gpu/drm/panel/panel-lvds.c if (lvds->backlight) { lvds 54 drivers/gpu/drm/panel/panel-lvds.c lvds->backlight->props.power = FB_BLANK_POWERDOWN; lvds 55 drivers/gpu/drm/panel/panel-lvds.c lvds->backlight->props.state |= BL_CORE_FBBLANK; lvds 56 drivers/gpu/drm/panel/panel-lvds.c backlight_update_status(lvds->backlight); lvds 64 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds = to_panel_lvds(panel); lvds 66 drivers/gpu/drm/panel/panel-lvds.c if (lvds->enable_gpio) lvds 67 drivers/gpu/drm/panel/panel-lvds.c gpiod_set_value_cansleep(lvds->enable_gpio, 0); lvds 69 drivers/gpu/drm/panel/panel-lvds.c if (lvds->supply) lvds 70 drivers/gpu/drm/panel/panel-lvds.c regulator_disable(lvds->supply); lvds 77 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds = to_panel_lvds(panel); lvds 79 drivers/gpu/drm/panel/panel-lvds.c if (lvds->supply) { lvds 82 drivers/gpu/drm/panel/panel-lvds.c err = regulator_enable(lvds->supply); lvds 84 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "failed to enable supply: %d\n", lvds 90 drivers/gpu/drm/panel/panel-lvds.c if (lvds->enable_gpio) lvds 91 drivers/gpu/drm/panel/panel-lvds.c gpiod_set_value_cansleep(lvds->enable_gpio, 1); lvds 98 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds = to_panel_lvds(panel); lvds 100 drivers/gpu/drm/panel/panel-lvds.c if (lvds->backlight) { lvds 101 drivers/gpu/drm/panel/panel-lvds.c lvds->backlight->props.state &= ~BL_CORE_FBBLANK; lvds 102 drivers/gpu/drm/panel/panel-lvds.c lvds->backlight->props.power = FB_BLANK_UNBLANK; lvds 103 drivers/gpu/drm/panel/panel-lvds.c backlight_update_status(lvds->backlight); lvds 111 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds = to_panel_lvds(panel); lvds 112 drivers/gpu/drm/panel/panel-lvds.c struct drm_connector *connector = lvds->panel.connector; lvds 115 drivers/gpu/drm/panel/panel-lvds.c mode = drm_mode_create(lvds->panel.drm); lvds 119 drivers/gpu/drm/panel/panel-lvds.c drm_display_mode_from_videomode(&lvds->video_mode, mode); lvds 123 drivers/gpu/drm/panel/panel-lvds.c connector->display_info.width_mm = lvds->width; lvds 124 drivers/gpu/drm/panel/panel-lvds.c connector->display_info.height_mm = lvds->height; lvds 126 drivers/gpu/drm/panel/panel-lvds.c &lvds->bus_format, 1); lvds 127 drivers/gpu/drm/panel/panel-lvds.c connector->display_info.bus_flags = lvds->data_mirror lvds 142 drivers/gpu/drm/panel/panel-lvds.c static int panel_lvds_parse_dt(struct panel_lvds *lvds) lvds 144 drivers/gpu/drm/panel/panel-lvds.c struct device_node *np = lvds->dev->of_node; lvds 151 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "%pOF: problems parsing panel-timing (%d)\n", lvds 156 drivers/gpu/drm/panel/panel-lvds.c videomode_from_timing(&timing, &lvds->video_mode); lvds 158 drivers/gpu/drm/panel/panel-lvds.c ret = of_property_read_u32(np, "width-mm", &lvds->width); lvds 160 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "%pOF: invalid or missing %s DT property\n", lvds 164 drivers/gpu/drm/panel/panel-lvds.c ret = of_property_read_u32(np, "height-mm", &lvds->height); lvds 166 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "%pOF: invalid or missing %s DT property\n", lvds 171 drivers/gpu/drm/panel/panel-lvds.c of_property_read_string(np, "label", &lvds->label); lvds 175 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "%pOF: invalid or missing %s DT property\n", lvds 181 drivers/gpu/drm/panel/panel-lvds.c lvds->bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG; lvds 183 drivers/gpu/drm/panel/panel-lvds.c lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; lvds 185 drivers/gpu/drm/panel/panel-lvds.c lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG; lvds 187 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "%pOF: invalid or missing %s DT property\n", lvds 192 drivers/gpu/drm/panel/panel-lvds.c lvds->data_mirror = of_property_read_bool(np, "data-mirror"); lvds 199 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds; lvds 202 drivers/gpu/drm/panel/panel-lvds.c lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); lvds 203 drivers/gpu/drm/panel/panel-lvds.c if (!lvds) lvds 206 drivers/gpu/drm/panel/panel-lvds.c lvds->dev = &pdev->dev; lvds 208 drivers/gpu/drm/panel/panel-lvds.c ret = panel_lvds_parse_dt(lvds); lvds 212 drivers/gpu/drm/panel/panel-lvds.c lvds->supply = devm_regulator_get_optional(lvds->dev, "power"); lvds 213 drivers/gpu/drm/panel/panel-lvds.c if (IS_ERR(lvds->supply)) { lvds 214 drivers/gpu/drm/panel/panel-lvds.c ret = PTR_ERR(lvds->supply); lvds 218 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "failed to request regulator: %d\n", lvds 223 drivers/gpu/drm/panel/panel-lvds.c lvds->supply = NULL; lvds 227 drivers/gpu/drm/panel/panel-lvds.c lvds->enable_gpio = devm_gpiod_get_optional(lvds->dev, "enable", lvds 229 drivers/gpu/drm/panel/panel-lvds.c if (IS_ERR(lvds->enable_gpio)) { lvds 230 drivers/gpu/drm/panel/panel-lvds.c ret = PTR_ERR(lvds->enable_gpio); lvds 231 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "failed to request %s GPIO: %d\n", lvds 236 drivers/gpu/drm/panel/panel-lvds.c lvds->reset_gpio = devm_gpiod_get_optional(lvds->dev, "reset", lvds 238 drivers/gpu/drm/panel/panel-lvds.c if (IS_ERR(lvds->reset_gpio)) { lvds 239 drivers/gpu/drm/panel/panel-lvds.c ret = PTR_ERR(lvds->reset_gpio); lvds 240 drivers/gpu/drm/panel/panel-lvds.c dev_err(lvds->dev, "failed to request %s GPIO: %d\n", lvds 245 drivers/gpu/drm/panel/panel-lvds.c lvds->backlight = devm_of_find_backlight(lvds->dev); lvds 246 drivers/gpu/drm/panel/panel-lvds.c if (IS_ERR(lvds->backlight)) lvds 247 drivers/gpu/drm/panel/panel-lvds.c return PTR_ERR(lvds->backlight); lvds 257 drivers/gpu/drm/panel/panel-lvds.c drm_panel_init(&lvds->panel); lvds 258 drivers/gpu/drm/panel/panel-lvds.c lvds->panel.dev = lvds->dev; lvds 259 drivers/gpu/drm/panel/panel-lvds.c lvds->panel.funcs = &panel_lvds_funcs; lvds 261 drivers/gpu/drm/panel/panel-lvds.c ret = drm_panel_add(&lvds->panel); lvds 265 drivers/gpu/drm/panel/panel-lvds.c dev_set_drvdata(lvds->dev, lvds); lvds 271 drivers/gpu/drm/panel/panel-lvds.c struct panel_lvds *lvds = dev_get_drvdata(&pdev->dev); lvds 273 drivers/gpu/drm/panel/panel-lvds.c drm_panel_remove(&lvds->panel); lvds 275 drivers/gpu/drm/panel/panel-lvds.c panel_lvds_disable(&lvds->panel); lvds 1640 drivers/gpu/drm/radeon/radeon_atombios.c struct radeon_encoder_atom_dig *lvds = NULL; lvds 1647 drivers/gpu/drm/radeon/radeon_atombios.c lvds = lvds 1650 drivers/gpu/drm/radeon/radeon_atombios.c if (!lvds) lvds 1653 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.clock = lvds 1655 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.hdisplay = lvds 1657 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.vdisplay = lvds 1659 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.htotal = lvds->native_mode.hdisplay + lvds 1661 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + lvds 1663 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + lvds 1665 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.vtotal = lvds->native_mode.vdisplay + lvds 1667 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + lvds 1669 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + lvds 1671 drivers/gpu/drm/radeon/radeon_atombios.c lvds->panel_pwr_delay = lvds 1673 drivers/gpu/drm/radeon/radeon_atombios.c lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; lvds 1677 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; lvds 1679 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; lvds 1681 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; lvds 1683 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; lvds 1685 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; lvds 1687 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); lvds 1688 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); lvds 1691 drivers/gpu/drm/radeon/radeon_atombios.c drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); lvds 1693 drivers/gpu/drm/radeon/radeon_atombios.c lvds->lcd_ss_id = lvds_info->info.ucSS_Id; lvds 1695 drivers/gpu/drm/radeon/radeon_atombios.c encoder->native_mode = lvds->native_mode; lvds 1698 drivers/gpu/drm/radeon/radeon_atombios.c lvds->linkb = true; lvds 1700 drivers/gpu/drm/radeon/radeon_atombios.c lvds->linkb = false; lvds 1753 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.width_mm = panel_res_record->usHSize; lvds 1754 drivers/gpu/drm/radeon/radeon_atombios.c lvds->native_mode.height_mm = panel_res_record->usVSize; lvds 1767 drivers/gpu/drm/radeon/radeon_atombios.c return lvds; lvds 1106 drivers/gpu/drm/radeon/radeon_combios.c struct radeon_encoder_lvds *lvds = NULL; lvds 1111 drivers/gpu/drm/radeon/radeon_combios.c lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); lvds 1113 drivers/gpu/drm/radeon/radeon_combios.c if (!lvds) lvds 1120 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_pwr_delay = 200; lvds 1121 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_vcc_delay = 2000; lvds 1123 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); lvds 1124 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; lvds 1125 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; lvds 1128 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vdisplay = lvds 1132 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vdisplay = lvds 1136 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.hdisplay = lvds 1140 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.hdisplay = lvds 1143 drivers/gpu/drm/radeon/radeon_combios.c if ((lvds->native_mode.hdisplay < 640) || lvds 1144 drivers/gpu/drm/radeon/radeon_combios.c (lvds->native_mode.vdisplay < 480)) { lvds 1145 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.hdisplay = 640; lvds 1146 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vdisplay = 480; lvds 1152 drivers/gpu/drm/radeon/radeon_combios.c lvds->use_bios_dividers = false; lvds 1154 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_ref_divider = lvds 1156 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_post_divider = (ppll_val >> 16) & 0x7; lvds 1157 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_fb_divider = ppll_val & 0x7ff; lvds 1159 drivers/gpu/drm/radeon/radeon_combios.c if ((lvds->panel_ref_divider != 0) && lvds 1160 drivers/gpu/drm/radeon/radeon_combios.c (lvds->panel_fb_divider > 3)) lvds 1161 drivers/gpu/drm/radeon/radeon_combios.c lvds->use_bios_dividers = true; lvds 1163 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_vcc_delay = 200; lvds 1166 drivers/gpu/drm/radeon/radeon_combios.c DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, lvds 1167 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vdisplay); lvds 1169 drivers/gpu/drm/radeon/radeon_combios.c return lvds; lvds 1181 drivers/gpu/drm/radeon/radeon_combios.c struct radeon_encoder_lvds *lvds = NULL; lvds 1186 drivers/gpu/drm/radeon/radeon_combios.c lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); lvds 1188 drivers/gpu/drm/radeon/radeon_combios.c if (!lvds) lvds 1197 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); lvds 1198 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); lvds 1200 drivers/gpu/drm/radeon/radeon_combios.c DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, lvds 1201 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vdisplay); lvds 1203 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); lvds 1204 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); lvds 1206 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); lvds 1207 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; lvds 1208 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; lvds 1210 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); lvds 1211 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); lvds 1212 drivers/gpu/drm/radeon/radeon_combios.c lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); lvds 1213 drivers/gpu/drm/radeon/radeon_combios.c if ((lvds->panel_ref_divider != 0) && lvds 1214 drivers/gpu/drm/radeon/radeon_combios.c (lvds->panel_fb_divider > 3)) lvds 1215 drivers/gpu/drm/radeon/radeon_combios.c lvds->use_bios_dividers = true; lvds 1218 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl = 0xff00; lvds 1220 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; lvds 1223 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; lvds 1227 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; lvds 1230 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; lvds 1233 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; lvds 1240 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; lvds 1243 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; lvds 1246 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; lvds 1249 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; lvds 1251 drivers/gpu/drm/radeon/radeon_combios.c lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); lvds 1258 drivers/gpu/drm/radeon/radeon_combios.c if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && lvds 1259 drivers/gpu/drm/radeon/radeon_combios.c (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { lvds 1262 drivers/gpu/drm/radeon/radeon_combios.c if (hss > lvds->native_mode.hdisplay) lvds 1265 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.htotal = lvds->native_mode.hdisplay + lvds 1267 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + lvds 1269 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + lvds 1272 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vtotal = lvds->native_mode.vdisplay + lvds 1274 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + lvds 1276 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + lvds 1279 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; lvds 1280 drivers/gpu/drm/radeon/radeon_combios.c lvds->native_mode.flags = 0; lvds 1282 drivers/gpu/drm/radeon/radeon_combios.c drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); lvds 1288 drivers/gpu/drm/radeon/radeon_combios.c lvds = radeon_legacy_get_lvds_info_from_regs(rdev); lvds 1291 drivers/gpu/drm/radeon/radeon_combios.c if (lvds) lvds 1292 drivers/gpu/drm/radeon/radeon_combios.c encoder->native_mode = lvds->native_mode; lvds 1293 drivers/gpu/drm/radeon/radeon_combios.c return lvds; lvds 799 drivers/gpu/drm/radeon/radeon_legacy_crtc.c struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; lvds 800 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (lvds) { lvds 801 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (lvds->use_bios_dividers) { lvds 802 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll_ref_div = lvds->panel_ref_divider; lvds 803 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll_fb_post_div = (lvds->panel_fb_divider | lvds 804 drivers/gpu/drm/radeon/radeon_legacy_crtc.c (lvds->panel_post_divider << 16)); lvds 69 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; lvds 70 drivers/gpu/drm/radeon/radeon_legacy_encoders.c panel_pwr_delay = lvds->panel_pwr_delay; lvds 71 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (lvds->bl_dev) lvds 72 drivers/gpu/drm/radeon/radeon_legacy_encoders.c backlight_level = lvds->backlight_level; lvds 74 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; lvds 75 drivers/gpu/drm/radeon/radeon_legacy_encoders.c panel_pwr_delay = lvds->panel_pwr_delay; lvds 76 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (lvds->bl_dev) lvds 77 drivers/gpu/drm/radeon/radeon_legacy_encoders.c backlight_level = lvds->backlight_level; lvds 150 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; lvds 151 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->dpms_mode = mode; lvds 153 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; lvds 154 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->dpms_mode = mode; lvds 207 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; lvds 208 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (lvds) { lvds 209 drivers/gpu/drm/radeon/radeon_legacy_encoders.c DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); lvds 210 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_gen_cntl = lvds->lvds_gen_cntl; lvds 213 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | lvds 214 drivers/gpu/drm/radeon/radeon_legacy_encoders.c (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); lvds 301 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; lvds 302 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (lvds->backlight_level > 0) lvds 303 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dpms_mode = lvds->dpms_mode; lvds 306 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->backlight_level = level; lvds 308 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; lvds 309 drivers/gpu/drm/radeon/radeon_legacy_encoders.c if (lvds->backlight_level > 0) lvds 310 drivers/gpu/drm/radeon/radeon_legacy_encoders.c dpms_mode = lvds->dpms_mode; lvds 313 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->backlight_level = level; lvds 439 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; lvds 440 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->bl_dev = bd; lvds 442 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; lvds 443 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->bl_dev = bd; lvds 470 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; lvds 471 drivers/gpu/drm/radeon/radeon_legacy_encoders.c bd = lvds->bl_dev; lvds 472 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->bl_dev = NULL; lvds 474 drivers/gpu/drm/radeon/radeon_legacy_encoders.c struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; lvds 475 drivers/gpu/drm/radeon/radeon_legacy_encoders.c bd = lvds->bl_dev; lvds 476 drivers/gpu/drm/radeon/radeon_legacy_encoders.c lvds->bl_dev = NULL; lvds 105 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_DTB(lvds, r8a7790); lvds 106 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_DTB(lvds, r8a7791); lvds 107 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_DTB(lvds, r8a7793); lvds 108 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_DTB(lvds, r8a7795); lvds 109 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_DTB(lvds, r8a7796); lvds 112 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_OVERLAY(lvds, r8a7790), lvds 113 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_OVERLAY(lvds, r8a7791), lvds 114 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_OVERLAY(lvds, r8a7793), lvds 115 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_OVERLAY(lvds, r8a7795), lvds 116 drivers/gpu/drm/rcar-du/rcar_du_of.c RCAR_DU_OF_OVERLAY(lvds, r8a7796), lvds 122 drivers/gpu/drm/rcar-du/rcar_du_of.c static void __init rcar_du_of_lvds_patch_one(struct device_node *lvds, lvds 148 drivers/gpu/drm/rcar-du/rcar_du_of.c ret = rcar_du_of_add_property(&rcar_du_lvds_changeset, lvds, lvds 167 drivers/gpu/drm/rcar-du/rcar_du_of.c endpoint = of_graph_get_endpoint_by_regs(lvds, i, 0); lvds 244 drivers/gpu/drm/rcar-du/rcar_du_of.c struct lvds_of_data *lvds = &lvds_data[i]; lvds 256 drivers/gpu/drm/rcar-du/rcar_du_of.c &lvds->clkspec); lvds 262 drivers/gpu/drm/rcar-du/rcar_du_of.c lvds->local = of_graph_get_endpoint_by_regs(du_node, port, 0); lvds 263 drivers/gpu/drm/rcar-du/rcar_du_of.c if (!lvds->local) lvds 266 drivers/gpu/drm/rcar-du/rcar_du_of.c lvds->remote = of_graph_get_remote_endpoint(lvds->local); lvds 267 drivers/gpu/drm/rcar-du/rcar_du_of.c if (!lvds->remote) lvds 274 drivers/gpu/drm/rcar-du/rcar_du_of.c of_address_to_resource(du_node, index, &lvds->res); lvds 48 drivers/gpu/drm/rcar-du/rcar_lvds.c void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq); lvds 81 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) lvds 83 drivers/gpu/drm/rcar-du/rcar_lvds.c iowrite32(data, lvds->mmio + reg); lvds 92 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = connector_to_rcar_lvds(connector); lvds 94 drivers/gpu/drm/rcar-du/rcar_lvds.c return drm_panel_get_modes(lvds->panel); lvds 100 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = connector_to_rcar_lvds(connector); lvds 110 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, "connector: empty modes list\n"); lvds 149 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq) lvds 162 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, val); lvds 165 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq) lvds 178 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, val); lvds 190 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, lvds 314 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, lvds 321 drivers/gpu/drm/rcar-du/rcar_lvds.c static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, lvds 327 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll, lvds 329 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll, lvds 331 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, lvds 344 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr); lvds 351 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL | lvds 354 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDDIV, 0); lvds 357 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq) lvds 359 drivers/gpu/drm/rcar-du/rcar_lvds.c __rcar_lvds_pll_setup_d3_e3(lvds, freq, false); lvds 368 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 371 drivers/gpu/drm/rcar-du/rcar_lvds.c if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))) lvds 374 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq); lvds 376 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = clk_prepare_enable(lvds->clocks.mod); lvds 380 drivers/gpu/drm/rcar-du/rcar_lvds.c __rcar_lvds_pll_setup_d3_e3(lvds, freq, true); lvds 388 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 390 drivers/gpu/drm/rcar-du/rcar_lvds.c if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))) lvds 393 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, "disabling LVDS PLL\n"); lvds 395 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, 0); lvds 397 drivers/gpu/drm/rcar-du/rcar_lvds.c clk_disable_unprepare(lvds->clocks.mod); lvds 407 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 408 drivers/gpu/drm/rcar-du/rcar_lvds.c const struct drm_display_mode *mode = &lvds->display_mode; lvds 413 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = clk_prepare_enable(lvds->clocks.mod); lvds 418 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->dual_link && lvds->companion) lvds 419 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->companion->funcs->enable(lvds->companion); lvds 429 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO | lvds 433 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES) lvds 440 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCHCR, lvdhcr); lvds 442 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) { lvds 447 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDSTRIPE, lvds 448 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->dual_link ? LVDSTRIPE_ST_ON : 0); lvds 455 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->dual_link || lvds->companion) lvds 456 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->info->pll_setup(lvds, mode->clock * 1000); lvds 459 drivers/gpu/drm/rcar-du/rcar_lvds.c lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT; lvds 461 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->bridge.encoder) { lvds 466 drivers/gpu/drm/rcar-du/rcar_lvds.c if (drm_crtc_index(lvds->bridge.encoder->crtc) == 2) lvds 470 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds 473 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR1, lvds 477 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->gen < 3) { lvds 480 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds 483 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { lvds 489 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds 492 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) { lvds 495 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds 498 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) { lvds 504 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD)) lvds 505 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds 508 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { lvds 515 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, lvdcr0); lvds 517 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->panel) { lvds 518 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_panel_prepare(lvds->panel); lvds 519 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_panel_enable(lvds->panel); lvds 525 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 527 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->panel) { lvds 528 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_panel_disable(lvds->panel); lvds 529 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_panel_unprepare(lvds->panel); lvds 532 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR0, 0); lvds 533 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDCR1, 0); lvds 534 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_write(lvds, LVDPLLCR, 0); lvds 537 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->dual_link && lvds->companion) lvds 538 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->companion->funcs->disable(lvds->companion); lvds 540 drivers/gpu/drm/rcar-du/rcar_lvds.c clk_disable_unprepare(lvds->clocks.mod); lvds 547 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 555 drivers/gpu/drm/rcar-du/rcar_lvds.c min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000; lvds 561 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds) lvds 563 drivers/gpu/drm/rcar-du/rcar_lvds.c struct drm_display_info *info = &lvds->connector.display_info; lvds 570 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->panel) lvds 574 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_err(lvds->dev, "no LVDS bus format reported\n"); lvds 587 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n", lvds 595 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->mode = mode; lvds 602 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 604 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->display_mode = *adjusted_mode; lvds 606 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_get_lvds_mode(lvds); lvds 611 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 612 drivers/gpu/drm/rcar-du/rcar_lvds.c struct drm_connector *connector = &lvds->connector; lvds 617 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->next_bridge) lvds 618 drivers/gpu/drm/rcar-du/rcar_lvds.c return drm_bridge_attach(bridge->encoder, lvds->next_bridge, lvds 622 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->panel) lvds 636 drivers/gpu/drm/rcar-du/rcar_lvds.c return drm_panel_attach(lvds->panel, connector); lvds 641 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 643 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->panel) lvds 644 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_panel_detach(lvds->panel); lvds 658 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); lvds 660 drivers/gpu/drm/rcar-du/rcar_lvds.c return lvds->dual_link; lvds 668 drivers/gpu/drm/rcar-du/rcar_lvds.c static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds) lvds 672 drivers/gpu/drm/rcar-du/rcar_lvds.c struct device *dev = lvds->dev; lvds 691 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->companion = of_drm_find_bridge(companion); lvds 692 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->companion) { lvds 705 drivers/gpu/drm/rcar-du/rcar_lvds.c static int rcar_lvds_parse_dt(struct rcar_lvds *lvds) lvds 714 drivers/gpu/drm/rcar-du/rcar_lvds.c local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0); lvds 716 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, "unconnected port@1\n"); lvds 727 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output); lvds 733 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_dbg(lvds->dev, "connected entity %pOF is disabled\n", lvds 754 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->next_bridge = of_drm_find_bridge(remote); lvds 755 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->next_bridge) { lvds 760 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) lvds 761 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->dual_link = lvds->next_bridge->timings lvds 762 drivers/gpu/drm/rcar-du/rcar_lvds.c ? lvds->next_bridge->timings->dual_link lvds 765 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->panel = of_drm_find_panel(remote); lvds 766 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->panel)) { lvds 767 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = PTR_ERR(lvds->panel); lvds 772 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->dual_link) lvds 773 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = rcar_lvds_parse_dt_companion(lvds); lvds 786 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL) lvds 792 drivers/gpu/drm/rcar-du/rcar_lvds.c static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name, lvds 797 drivers/gpu/drm/rcar-du/rcar_lvds.c clk = devm_clk_get(lvds->dev, name); lvds 805 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_err(lvds->dev, "failed to get %s clock\n", lvds 811 drivers/gpu/drm/rcar-du/rcar_lvds.c static int rcar_lvds_get_clocks(struct rcar_lvds *lvds) lvds 813 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false); lvds 814 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.mod)) lvds 815 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.mod); lvds 820 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) lvds 823 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true); lvds 824 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.extal)) lvds 825 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.extal); lvds 827 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true); lvds 828 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.dotclkin[0])) lvds 829 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.dotclkin[0]); lvds 831 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true); lvds 832 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.dotclkin[1])) lvds 833 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.dotclkin[1]); lvds 836 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] && lvds 837 drivers/gpu/drm/rcar-du/rcar_lvds.c !lvds->clocks.dotclkin[1]) { lvds 838 drivers/gpu/drm/rcar-du/rcar_lvds.c dev_err(lvds->dev, lvds 863 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds; lvds 867 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); lvds 868 drivers/gpu/drm/rcar-du/rcar_lvds.c if (lvds == NULL) lvds 871 drivers/gpu/drm/rcar-du/rcar_lvds.c platform_set_drvdata(pdev, lvds); lvds 873 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->dev = &pdev->dev; lvds 874 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->info = of_device_get_match_data(&pdev->dev); lvds 878 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->info = attr->data; lvds 880 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = rcar_lvds_parse_dt(lvds); lvds 884 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->bridge.driver_private = lvds; lvds 885 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->bridge.funcs = &rcar_lvds_bridge_ops; lvds 886 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->bridge.of_node = pdev->dev.of_node; lvds 889 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->mmio = devm_ioremap_resource(&pdev->dev, mem); lvds 890 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->mmio)) lvds 891 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->mmio); lvds 893 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = rcar_lvds_get_clocks(lvds); lvds 897 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_bridge_add(&lvds->bridge); lvds 904 drivers/gpu/drm/rcar-du/rcar_lvds.c struct rcar_lvds *lvds = platform_get_drvdata(pdev); lvds 906 drivers/gpu/drm/rcar-du/rcar_lvds.c drm_bridge_remove(&lvds->bridge); lvds 69 drivers/gpu/drm/rockchip/rockchip_lvds.c static inline void lvds_writel(struct rockchip_lvds *lvds, u32 offset, u32 val) lvds 71 drivers/gpu/drm/rockchip/rockchip_lvds.c writel_relaxed(val, lvds->regs + offset); lvds 72 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->output == DISPLAY_OUTPUT_LVDS) lvds 74 drivers/gpu/drm/rockchip/rockchip_lvds.c writel_relaxed(val, lvds->regs + offset + lvds->soc_data->ch1_offset); lvds 101 drivers/gpu/drm/rockchip/rockchip_lvds.c static int rockchip_lvds_poweron(struct rockchip_lvds *lvds) lvds 106 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = clk_enable(lvds->pclk); lvds 108 drivers/gpu/drm/rockchip/rockchip_lvds.c DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); lvds 111 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = pm_runtime_get_sync(lvds->dev); lvds 113 drivers/gpu/drm/rockchip/rockchip_lvds.c DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); lvds 114 drivers/gpu/drm/rockchip/rockchip_lvds.c clk_disable(lvds->pclk); lvds 120 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->output == DISPLAY_OUTPUT_RGB) { lvds 123 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val); lvds 124 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG2, lvds 126 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG4, lvds 133 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG5, lvds 143 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val); lvds 144 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG1, lvds 151 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG2, lvds 160 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00); lvds 161 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00); lvds 163 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG3, RK3288_LVDS_PLL_FBDIV_REG3(0x46)); lvds 164 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REGD, RK3288_LVDS_PLL_PREDIV_REGD(0x0a)); lvds 165 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CH0_REG20, RK3288_LVDS_CH0_REG20_LSB); lvds 167 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); lvds 168 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); lvds 173 drivers/gpu/drm/rockchip/rockchip_lvds.c static void rockchip_lvds_poweroff(struct rockchip_lvds *lvds) lvds 178 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE); lvds 179 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE); lvds 182 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val); lvds 184 drivers/gpu/drm/rockchip/rockchip_lvds.c DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret); lvds 186 drivers/gpu/drm/rockchip/rockchip_lvds.c pm_runtime_put(lvds->dev); lvds 187 drivers/gpu/drm/rockchip/rockchip_lvds.c clk_disable(lvds->pclk); lvds 200 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = connector_to_lvds(connector); lvds 201 drivers/gpu/drm/rockchip/rockchip_lvds.c struct drm_panel *panel = lvds->panel; lvds 214 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = encoder_to_lvds(encoder); lvds 221 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->output == DISPLAY_OUTPUT_RGB) lvds 222 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->pins && !IS_ERR(lvds->pins->default_state)) lvds 223 drivers/gpu/drm/rockchip/rockchip_lvds.c pinctrl_select_state(lvds->pins->p, lvds 224 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pins->default_state); lvds 225 drivers/gpu/drm/rockchip/rockchip_lvds.c val = lvds->format | LVDS_CH0_EN; lvds 226 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->output == DISPLAY_OUTPUT_RGB) lvds 228 drivers/gpu/drm/rockchip/rockchip_lvds.c else if (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS) lvds 236 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val); lvds 238 drivers/gpu/drm/rockchip/rockchip_lvds.c DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret); lvds 243 drivers/gpu/drm/rockchip/rockchip_lvds.c static int rockchip_lvds_set_vop_source(struct rockchip_lvds *lvds, lvds 249 drivers/gpu/drm/rockchip/rockchip_lvds.c if (!lvds->soc_data->has_vop_sel) lvds 252 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder); lvds 260 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con6, val); lvds 282 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = encoder_to_lvds(encoder); lvds 286 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_panel_prepare(lvds->panel); lvds 287 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = rockchip_lvds_poweron(lvds); lvds 289 drivers/gpu/drm/rockchip/rockchip_lvds.c DRM_DEV_ERROR(lvds->dev, "failed to power on lvds: %d\n", ret); lvds 290 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_panel_unprepare(lvds->panel); lvds 293 drivers/gpu/drm/rockchip/rockchip_lvds.c rockchip_lvds_set_vop_source(lvds, encoder); lvds 294 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_panel_enable(lvds->panel); lvds 299 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = encoder_to_lvds(encoder); lvds 301 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_panel_disable(lvds->panel); lvds 302 drivers/gpu/drm/rockchip/rockchip_lvds.c rockchip_lvds_poweroff(lvds); lvds 303 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_panel_unprepare(lvds->panel); lvds 336 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = dev_get_drvdata(dev); lvds 346 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->drm_dev = drm_dev; lvds 357 drivers/gpu/drm/rockchip/rockchip_lvds.c &lvds->panel, &lvds->bridge); lvds 372 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->panel) lvds 373 drivers/gpu/drm/rockchip/rockchip_lvds.c remote = lvds->panel->dev->of_node; lvds 375 drivers/gpu/drm/rockchip/rockchip_lvds.c remote = lvds->bridge->of_node; lvds 378 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->output = DISPLAY_OUTPUT_RGB; lvds 380 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->output = lvds_name_to_output(name); lvds 382 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->output < 0) { lvds 384 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = lvds->output; lvds 390 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->format = LVDS_VESA_18; lvds 392 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->format = lvds_name_to_format(name); lvds 394 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->format < 0) { lvds 396 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = lvds->format; lvds 400 drivers/gpu/drm/rockchip/rockchip_lvds.c encoder = &lvds->encoder; lvds 414 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->panel) { lvds 415 drivers/gpu/drm/rockchip/rockchip_lvds.c connector = &lvds->connector; lvds 436 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = drm_panel_attach(lvds->panel, connector); lvds 443 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = drm_bridge_attach(encoder, lvds->bridge, NULL); lvds 472 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = dev_get_drvdata(dev); lvds 474 drivers/gpu/drm/rockchip/rockchip_lvds.c rockchip_lvds_encoder_disable(&lvds->encoder); lvds 475 drivers/gpu/drm/rockchip/rockchip_lvds.c if (lvds->panel) lvds 476 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_panel_detach(lvds->panel); lvds 478 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_connector_cleanup(&lvds->connector); lvds 479 drivers/gpu/drm/rockchip/rockchip_lvds.c drm_encoder_cleanup(&lvds->encoder); lvds 490 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds; lvds 498 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); lvds 499 drivers/gpu/drm/rockchip/rockchip_lvds.c if (!lvds) lvds 502 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->dev = dev; lvds 506 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->soc_data = match->data; lvds 509 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->regs = devm_ioremap_resource(&pdev->dev, res); lvds 510 drivers/gpu/drm/rockchip/rockchip_lvds.c if (IS_ERR(lvds->regs)) lvds 511 drivers/gpu/drm/rockchip/rockchip_lvds.c return PTR_ERR(lvds->regs); lvds 513 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pclk = devm_clk_get(&pdev->dev, "pclk_lvds"); lvds 514 drivers/gpu/drm/rockchip/rockchip_lvds.c if (IS_ERR(lvds->pclk)) { lvds 516 drivers/gpu/drm/rockchip/rockchip_lvds.c return PTR_ERR(lvds->pclk); lvds 519 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pins = devm_kzalloc(lvds->dev, sizeof(*lvds->pins), lvds 521 drivers/gpu/drm/rockchip/rockchip_lvds.c if (!lvds->pins) lvds 524 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pins->p = devm_pinctrl_get(lvds->dev); lvds 525 drivers/gpu/drm/rockchip/rockchip_lvds.c if (IS_ERR(lvds->pins->p)) { lvds 527 drivers/gpu/drm/rockchip/rockchip_lvds.c devm_kfree(lvds->dev, lvds->pins); lvds 528 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pins = NULL; lvds 530 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pins->default_state = lvds 531 drivers/gpu/drm/rockchip/rockchip_lvds.c pinctrl_lookup_state(lvds->pins->p, "lcdc"); lvds 532 drivers/gpu/drm/rockchip/rockchip_lvds.c if (IS_ERR(lvds->pins->default_state)) { lvds 534 drivers/gpu/drm/rockchip/rockchip_lvds.c devm_kfree(lvds->dev, lvds->pins); lvds 535 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->pins = NULL; lvds 539 drivers/gpu/drm/rockchip/rockchip_lvds.c lvds->grf = syscon_regmap_lookup_by_phandle(dev->of_node, lvds 541 drivers/gpu/drm/rockchip/rockchip_lvds.c if (IS_ERR(lvds->grf)) { lvds 543 drivers/gpu/drm/rockchip/rockchip_lvds.c return PTR_ERR(lvds->grf); lvds 546 drivers/gpu/drm/rockchip/rockchip_lvds.c dev_set_drvdata(dev, lvds); lvds 548 drivers/gpu/drm/rockchip/rockchip_lvds.c ret = clk_prepare(lvds->pclk); lvds 556 drivers/gpu/drm/rockchip/rockchip_lvds.c clk_unprepare(lvds->pclk); lvds 564 drivers/gpu/drm/rockchip/rockchip_lvds.c struct rockchip_lvds *lvds = dev_get_drvdata(&pdev->dev); lvds 567 drivers/gpu/drm/rockchip/rockchip_lvds.c clk_unprepare(lvds->pclk); lvds 42 drivers/gpu/drm/sun4i/sun4i_lvds.c struct sun4i_lvds *lvds = lvds 45 drivers/gpu/drm/sun4i/sun4i_lvds.c return drm_panel_get_modes(lvds->panel); lvds 55 drivers/gpu/drm/sun4i/sun4i_lvds.c struct sun4i_lvds *lvds = drm_connector_to_sun4i_lvds(connector); lvds 57 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_panel_detach(lvds->panel); lvds 71 drivers/gpu/drm/sun4i/sun4i_lvds.c struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(encoder); lvds 75 drivers/gpu/drm/sun4i/sun4i_lvds.c if (lvds->panel) { lvds 76 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_panel_prepare(lvds->panel); lvds 77 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_panel_enable(lvds->panel); lvds 83 drivers/gpu/drm/sun4i/sun4i_lvds.c struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(encoder); lvds 87 drivers/gpu/drm/sun4i/sun4i_lvds.c if (lvds->panel) { lvds 88 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_panel_disable(lvds->panel); lvds 89 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_panel_unprepare(lvds->panel); lvds 106 drivers/gpu/drm/sun4i/sun4i_lvds.c struct sun4i_lvds *lvds; lvds 109 drivers/gpu/drm/sun4i/sun4i_lvds.c lvds = devm_kzalloc(drm->dev, sizeof(*lvds), GFP_KERNEL); lvds 110 drivers/gpu/drm/sun4i/sun4i_lvds.c if (!lvds) lvds 112 drivers/gpu/drm/sun4i/sun4i_lvds.c encoder = &lvds->encoder; lvds 115 drivers/gpu/drm/sun4i/sun4i_lvds.c &lvds->panel, &bridge); lvds 121 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_encoder_helper_add(&lvds->encoder, lvds 124 drivers/gpu/drm/sun4i/sun4i_lvds.c &lvds->encoder, lvds 134 drivers/gpu/drm/sun4i/sun4i_lvds.c lvds->encoder.possible_crtcs = drm_crtc_mask(&tcon->crtc->crtc); lvds 136 drivers/gpu/drm/sun4i/sun4i_lvds.c if (lvds->panel) { lvds 137 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_connector_helper_add(&lvds->connector, lvds 139 drivers/gpu/drm/sun4i/sun4i_lvds.c ret = drm_connector_init(drm, &lvds->connector, lvds 147 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_connector_attach_encoder(&lvds->connector, lvds 148 drivers/gpu/drm/sun4i/sun4i_lvds.c &lvds->encoder); lvds 150 drivers/gpu/drm/sun4i/sun4i_lvds.c ret = drm_panel_attach(lvds->panel, &lvds->connector); lvds 168 drivers/gpu/drm/sun4i/sun4i_lvds.c drm_encoder_cleanup(&lvds->encoder); lvds 1582 drivers/pinctrl/actions/pinctrl-s700.c [S700_MUX_LVDS] = FUNCTION(lvds), lvds 1427 drivers/pinctrl/actions/pinctrl-s900.c [S900_MUX_LVDS] = FUNCTION(lvds), lvds 207 drivers/video/fbdev/intelfb/intelfb.h u32 lvds; lvds 582 drivers/video/fbdev/intelfb/intelfbhw.c hw->lvds = INREG(LVDS); lvds 667 drivers/video/fbdev/intelfb/intelfbhw.c int lvds) lvds 810 drivers/video/fbdev/intelfb/intelfbhw.c printk(" LVDS: 0x%08x\n", hw->lvds);