MCTL              150 drivers/staging/most/dim2/hal.c 	while ((readl(&g.dim2->MCTL) & 1) != 1)
MCTL              153 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
MCTL              163 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
MCTL              181 drivers/staging/most/dim2/hal.c 	writel(0, &g.dim2->MCTL);   /* clear transfer complete */
MCTL               48 drivers/staging/most/dim2/reg.h 	u32 MCTL;        /* 0x38 */