lut0              211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 		REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
lut0              915 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	struct dc_rgb *lut0;
lut0              936 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		lut0 = params->tetrahedral_17.lut0;
lut0              940 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		lut_size0 = sizeof(params->tetrahedral_17.lut0)/
lut0              941 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 					sizeof(params->tetrahedral_17.lut0[0]);
lut0              945 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		lut0 = params->tetrahedral_9.lut0;
lut0              949 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		lut_size0 = sizeof(params->tetrahedral_9.lut0)/
lut0              950 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 				sizeof(params->tetrahedral_9.lut0[0]);
lut0              959 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		dpp20_set3dlut_ram12(dpp_base, lut0, lut_size0);
lut0              961 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 		dpp20_set3dlut_ram10(dpp_base, lut0, lut_size0);
lut0               80 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h 	int lut0;
lut0               92 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h 	struct dc_rgb lut0[1229];
lut0               98 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h 	struct dc_rgb lut0[183];