MCIF_WB_NB_PSTATE_CONTROL   80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
MCIF_WB_NB_PSTATE_CONTROL  243 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
MCIF_WB_NB_PSTATE_CONTROL  179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);
MCIF_WB_NB_PSTATE_CONTROL  183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);
MCIF_WB_NB_PSTATE_CONTROL  187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);
MCIF_WB_NB_PSTATE_CONTROL  191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);
MCIF_WB_NB_PSTATE_CONTROL   94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
MCIF_WB_NB_PSTATE_CONTROL  476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	uint32_t MCIF_WB_NB_PSTATE_CONTROL;\