MCIF_WB_BUF_4_ADDR_Y_OFFSET   75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB_BUF_4_ADDR_Y_OFFSET  131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
MCIF_WB_BUF_4_ADDR_Y_OFFSET  196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
MCIF_WB_BUF_4_ADDR_Y_OFFSET  238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
MCIF_WB_BUF_4_ADDR_Y_OFFSET  125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0);
MCIF_WB_BUF_4_ADDR_Y_OFFSET   89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB_BUF_4_ADDR_Y_OFFSET  235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
MCIF_WB_BUF_4_ADDR_Y_OFFSET  397 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
MCIF_WB_BUF_4_ADDR_Y_OFFSET  471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\