lt 192 arch/arm/include/asm/assembler.h .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo lt 449 arch/arm/include/asm/assembler.h .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo lt 441 arch/arm64/include/asm/assembler.h b.lt 9000f lt 63 arch/mips/include/asm/cpu-features.h #define __isa_range(ge, lt) \ lt 64 arch/mips/include/asm/cpu-features.h ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) lt 65 arch/mips/include/asm/cpu-features.h #define __isa_range_or_flag(ge, lt, flag) \ lt 66 arch/mips/include/asm/cpu-features.h (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) lt 259 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lt:8; lt 263 arch/mips/include/asm/octeon/cvmx-pci-defs.h uint32_t lt:8; lt 186 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h __BITFIELD_FIELD(uint32_t lt:1, lt 165 arch/mips/kernel/ptrace.c unsigned long lt[NUM_WATCH_REGS]; lt 174 arch/mips/kernel/ptrace.c __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]); lt 176 arch/mips/kernel/ptrace.c if (lt[i] & __UA_LIMIT) lt 180 arch/mips/kernel/ptrace.c if (lt[i] & 0xffffffff80000000UL) lt 183 arch/mips/kernel/ptrace.c if (lt[i] & __UA_LIMIT) lt 193 arch/mips/kernel/ptrace.c if (lt[i] & MIPS_WATCHLO_IRW) lt 195 arch/mips/kernel/ptrace.c child->thread.watch.mips3264.watchlo[i] = lt[i]; lt 56 arch/mips/pci/fixup-cobalt.c unsigned char lt; lt 67 arch/mips/pci/fixup-cobalt.c pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); lt 68 arch/mips/pci/fixup-cobalt.c if (lt < 64) lt 1108 arch/mips/pci/pcie-octeon.c } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)); lt 41 arch/x86/include/asm/alternative-asm.h .long \alt - . lt 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay) lt 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_dp *dp = lt->dp; lt 56 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_rdaux(dp->aux, DPCD_LS02, lt->stat, 6); lt 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_rdaux(dp->aux, DPCD_LS0C, <->pc2stat, 1); lt 63 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c lt->pc2stat = 0x00; lt 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c lt->stat, lt->pc2stat); lt 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c OUTP_TRACE(&dp->outp, "status %6ph", lt->stat); lt 74 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_drive(struct lt_state *lt, bool pc) lt 76 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_dp *dp = lt->dp; lt 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; lt 87 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3; lt 104 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c lt->conf[i] = (lpre << 3) | lvsw; lt 105 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); lt 108 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c i, lt->conf[i], lpc2); lt 126 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_wraux(dp->aux, DPCD_LC03(0), lt->conf, 4); lt 131 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_wraux(dp->aux, DPCD_LC0F, lt->pc2conf, 2); lt 140 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern) lt 142 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct nvkm_dp *dp = lt->dp; lt 155 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_eq(struct lt_state *lt) lt 160 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) lt 161 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_pattern(lt, 3); lt 163 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_pattern(lt, 2); lt 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_drive(lt, lt->pc2)) || lt 168 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_sense(lt, lt->pc2, 400)) lt 171 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); lt 172 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c for (i = 0; i < lt->dp->outp.ior->dp.nr && eq_done; i++) { lt 173 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; lt 186 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_cr(struct lt_state *lt) lt 189 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; lt 192 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_pattern(lt, 1); lt 195 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (nvkm_dp_train_drive(lt, false) || lt 196 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_sense(lt, false, 100)) lt 200 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c for (i = 0; i < lt->dp->outp.ior->dp.nr; i++) { lt 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; lt 204 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED) lt 210 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { lt 211 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; lt 226 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c struct lt_state lt = { lt 239 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; lt 242 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if ((lnkcmp = lt.dp->info.lnkcmp)) { lt 282 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c memset(lt.stat, 0x00, sizeof(lt.stat)); lt 283 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_dp_train_cr(<); lt 285 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ret = nvkm_dp_train_eq(<); lt 286 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_dp_train_pattern(<, 0); lt 405 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c ior->dp.mst = dp->lt.mst; lt 418 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c atomic_set(&dp->lt.done, 1); lt 441 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c atomic_set(&dp->lt.done, 0); lt 471 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c dataKBps, linkKBps, ior->dp.mst, dp->lt.mst); lt 472 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (linkKBps < dataKBps || ior->dp.mst != dp->lt.mst) { lt 502 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (retrain || !atomic_read(&dp->lt.done)) lt 531 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c atomic_set(&dp->lt.done, 0); lt 546 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (atomic_read(&dp->lt.done)) lt 675 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c atomic_set(&dp->lt.done, 0); lt 30 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h } lt; lt 240 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c dp->lt.mst = !!args->v0.state; lt 1046 drivers/hid/hid-wiimote-modules.c __s8 rx, ry, lx, ly, lt, rt; lt 1105 drivers/hid/hid-wiimote-modules.c lt = (ext[2] >> 2) & 0x18; lt 1106 drivers/hid/hid-wiimote-modules.c lt |= (ext[3] >> 5) & 0x07; lt 1111 drivers/hid/hid-wiimote-modules.c lt <<= 1; lt 1118 drivers/hid/hid-wiimote-modules.c input_report_abs(wdata->extension.input, ABS_HAT3Y, lt); lt 230 drivers/infiniband/core/verbs.c enum rdma_transport_type lt; lt 234 drivers/infiniband/core/verbs.c lt = rdma_node_get_transport(device->node_type); lt 235 drivers/infiniband/core/verbs.c if (lt == RDMA_TRANSPORT_IB) lt 50 drivers/media/platform/rockchip/rga/rga-hw.c struct rga_addr_offset *lt, *lb, *rt, *rb; lt 54 drivers/media/platform/rockchip/rga/rga-hw.c lt = &offsets.left_top; lt 65 drivers/media/platform/rockchip/rga/rga-hw.c lt->y_off = y * frm->stride + x * pixel_width; lt 66 drivers/media/platform/rockchip/rga/rga-hw.c lt->u_off = lt 68 drivers/media/platform/rockchip/rga/rga-hw.c lt->v_off = lt->u_off + frm->width * frm->height / uv_factor; lt 70 drivers/media/platform/rockchip/rga/rga-hw.c lb->y_off = lt->y_off + (h - 1) * frm->stride; lt 71 drivers/media/platform/rockchip/rga/rga-hw.c lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride; lt 72 drivers/media/platform/rockchip/rga/rga-hw.c lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride; lt 74 drivers/media/platform/rockchip/rga/rga-hw.c rt->y_off = lt->y_off + (w - 1) * pixel_width; lt 75 drivers/media/platform/rockchip/rga/rga-hw.c rt->u_off = lt->u_off + w / x_div - 1; lt 76 drivers/media/platform/rockchip/rga/rga-hw.c rt->v_off = lt->v_off + w / x_div - 1; lt 989 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 999 drivers/mtd/nand/raw/marvell_nand.c unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); lt 1024 drivers/mtd/nand/raw/marvell_nand.c lt->data_bytes + oob_bytes); lt 1025 drivers/mtd/nand/raw/marvell_nand.c memcpy(data_buf, nfc->dma_buf, lt->data_bytes); lt 1026 drivers/mtd/nand/raw/marvell_nand.c memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes); lt 1028 drivers/mtd/nand/raw/marvell_nand.c marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes); lt 1047 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1048 drivers/mtd/nand/raw/marvell_nand.c unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; lt 1071 drivers/mtd/nand/raw/marvell_nand.c lt->data_bytes, true, page); lt 1101 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1111 drivers/mtd/nand/raw/marvell_nand.c unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0); lt 1130 drivers/mtd/nand/raw/marvell_nand.c memcpy(nfc->dma_buf, data_buf, lt->data_bytes); lt 1131 drivers/mtd/nand/raw/marvell_nand.c memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes); lt 1132 drivers/mtd/nand/raw/marvell_nand.c marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes + lt 1133 drivers/mtd/nand/raw/marvell_nand.c lt->ecc_bytes + lt->spare_bytes); lt 1135 drivers/mtd/nand/raw/marvell_nand.c marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes); lt 1195 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1197 drivers/mtd/nand/raw/marvell_nand.c int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; lt 1198 drivers/mtd/nand/raw/marvell_nand.c int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + lt 1199 drivers/mtd/nand/raw/marvell_nand.c lt->last_spare_bytes; lt 1200 drivers/mtd/nand/raw/marvell_nand.c int data_len = lt->data_bytes; lt 1201 drivers/mtd/nand/raw/marvell_nand.c int spare_len = lt->spare_bytes; lt 1202 drivers/mtd/nand/raw/marvell_nand.c int ecc_len = lt->ecc_bytes; lt 1212 drivers/mtd/nand/raw/marvell_nand.c for (chunk = 0; chunk < lt->nchunks; chunk++) { lt 1214 drivers/mtd/nand/raw/marvell_nand.c if (chunk >= lt->full_chunk_cnt) { lt 1215 drivers/mtd/nand/raw/marvell_nand.c data_len = lt->last_data_bytes; lt 1216 drivers/mtd/nand/raw/marvell_nand.c spare_len = lt->last_spare_bytes; lt 1217 drivers/mtd/nand/raw/marvell_nand.c ecc_len = lt->last_ecc_bytes; lt 1222 drivers/mtd/nand/raw/marvell_nand.c buf + (lt->data_bytes * chunk), lt 1226 drivers/mtd/nand/raw/marvell_nand.c nand_read_data_op(chip, oob + (lt->spare_bytes * chunk), lt 1231 drivers/mtd/nand/raw/marvell_nand.c (ALIGN(lt->ecc_bytes, 32) * chunk), lt 1245 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1271 drivers/mtd/nand/raw/marvell_nand.c else if (chunk < lt->nchunks - 1) lt 1310 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1311 drivers/mtd/nand/raw/marvell_nand.c int data_len = lt->data_bytes, spare_len = lt->spare_bytes; lt 1329 drivers/mtd/nand/raw/marvell_nand.c for (chunk = 0; chunk < lt->nchunks; chunk++) { lt 1331 drivers/mtd/nand/raw/marvell_nand.c if (chunk >= lt->full_chunk_cnt) { lt 1332 drivers/mtd/nand/raw/marvell_nand.c data_len = lt->last_data_bytes; lt 1333 drivers/mtd/nand/raw/marvell_nand.c spare_len = lt->last_spare_bytes; lt 1372 drivers/mtd/nand/raw/marvell_nand.c for (chunk = 0; chunk < lt->nchunks; chunk++) { lt 1381 drivers/mtd/nand/raw/marvell_nand.c data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes + lt 1382 drivers/mtd/nand/raw/marvell_nand.c lt->ecc_bytes); lt 1384 drivers/mtd/nand/raw/marvell_nand.c (chunk < lt->full_chunk_cnt ? lt->data_bytes : lt 1385 drivers/mtd/nand/raw/marvell_nand.c lt->last_data_bytes); lt 1387 drivers/mtd/nand/raw/marvell_nand.c (chunk < lt->full_chunk_cnt ? lt->spare_bytes : lt 1388 drivers/mtd/nand/raw/marvell_nand.c lt->last_spare_bytes); lt 1390 drivers/mtd/nand/raw/marvell_nand.c data_off = chunk * lt->data_bytes; lt 1391 drivers/mtd/nand/raw/marvell_nand.c spare_off = chunk * lt->spare_bytes; lt 1392 drivers/mtd/nand/raw/marvell_nand.c ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) + lt 1393 drivers/mtd/nand/raw/marvell_nand.c lt->last_spare_bytes + lt 1394 drivers/mtd/nand/raw/marvell_nand.c (chunk * (lt->ecc_bytes + 2)); lt 1396 drivers/mtd/nand/raw/marvell_nand.c data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes : lt 1397 drivers/mtd/nand/raw/marvell_nand.c lt->last_data_bytes; lt 1398 drivers/mtd/nand/raw/marvell_nand.c spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes : lt 1399 drivers/mtd/nand/raw/marvell_nand.c lt->last_spare_bytes; lt 1400 drivers/mtd/nand/raw/marvell_nand.c ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes : lt 1401 drivers/mtd/nand/raw/marvell_nand.c lt->last_ecc_bytes; lt 1409 drivers/mtd/nand/raw/marvell_nand.c if (lt->writesize == 2048 && lt->strength == 8) { lt 1451 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1452 drivers/mtd/nand/raw/marvell_nand.c int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes; lt 1453 drivers/mtd/nand/raw/marvell_nand.c int data_len = lt->data_bytes; lt 1454 drivers/mtd/nand/raw/marvell_nand.c int spare_len = lt->spare_bytes; lt 1455 drivers/mtd/nand/raw/marvell_nand.c int ecc_len = lt->ecc_bytes; lt 1457 drivers/mtd/nand/raw/marvell_nand.c int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) + lt 1458 drivers/mtd/nand/raw/marvell_nand.c lt->last_spare_bytes; lt 1465 drivers/mtd/nand/raw/marvell_nand.c for (chunk = 0; chunk < lt->nchunks; chunk++) { lt 1466 drivers/mtd/nand/raw/marvell_nand.c if (chunk >= lt->full_chunk_cnt) { lt 1467 drivers/mtd/nand/raw/marvell_nand.c data_len = lt->last_data_bytes; lt 1468 drivers/mtd/nand/raw/marvell_nand.c spare_len = lt->last_spare_bytes; lt 1469 drivers/mtd/nand/raw/marvell_nand.c ecc_len = lt->last_ecc_bytes; lt 1477 drivers/mtd/nand/raw/marvell_nand.c nand_write_data_op(chip, buf + (chunk * lt->data_bytes), lt 1508 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1525 drivers/mtd/nand/raw/marvell_nand.c if (lt->nchunks == 1) lt 1535 drivers/mtd/nand/raw/marvell_nand.c } else if (chunk < lt->nchunks - 1) { lt 1542 drivers/mtd/nand/raw/marvell_nand.c if (chunk == lt->nchunks - 1) lt 1567 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 1570 drivers/mtd/nand/raw/marvell_nand.c int data_len = lt->data_bytes; lt 1571 drivers/mtd/nand/raw/marvell_nand.c int spare_len = lt->spare_bytes; lt 1582 drivers/mtd/nand/raw/marvell_nand.c for (chunk = 0; chunk < lt->nchunks; chunk++) { lt 1583 drivers/mtd/nand/raw/marvell_nand.c if (chunk >= lt->full_chunk_cnt) { lt 1584 drivers/mtd/nand/raw/marvell_nand.c data_len = lt->last_data_bytes; lt 1585 drivers/mtd/nand/raw/marvell_nand.c spare_len = lt->last_spare_bytes; lt 2128 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 2133 drivers/mtd/nand/raw/marvell_nand.c oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) + lt 2134 drivers/mtd/nand/raw/marvell_nand.c lt->last_ecc_bytes; lt 2144 drivers/mtd/nand/raw/marvell_nand.c const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout; lt 2153 drivers/mtd/nand/raw/marvell_nand.c if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K) lt 2158 drivers/mtd/nand/raw/marvell_nand.c oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) + lt 2159 drivers/mtd/nand/raw/marvell_nand.c lt->last_spare_bytes - oobregion->offset; lt 648 drivers/net/ethernet/cavium/liquidio/lio_main.c struct lio_time *lt; lt 658 drivers/net/ethernet/cavium/liquidio/lio_main.c lt = (struct lio_time *)sc->virtdptr; lt 662 drivers/net/ethernet/cavium/liquidio/lio_main.c lt->sec = ts.tv_sec; lt 663 drivers/net/ethernet/cavium/liquidio/lio_main.c lt->nsec = ts.tv_nsec; lt 664 drivers/net/ethernet/cavium/liquidio/lio_main.c octeon_swap_8B_data((u64 *)lt, (sizeof(struct lio_time)) / 8); lt 738 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int lid, lt, ld, fl; lt 750 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c for (lt = 0; lt < NPC_MAX_LT; lt++) { lt 752 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c SET_KEX_LD(NIX_INTF_RX, lid, lt, ld, lt 754 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c [lid][lt][ld]); lt 756 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c SET_KEX_LD(NIX_INTF_TX, lid, lt, ld, lt 758 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c [lid][lt][ld]); lt 2150 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c #define GET_KEX_LD(intf, lid, lt, ld) \ lt 2152 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)) lt 2161 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c int lid, lt, ld, fl; lt 2166 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c for (lt = 0; lt < NPC_MAX_LT; lt++) { lt 2168 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] = lt 2169 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c GET_KEX_LD(NIX_INTF_RX, lid, lt, ld); lt 2170 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] = lt 2171 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c GET_KEX_LD(NIX_INTF_TX, lid, lt, ld); lt 275 drivers/power/supply/bq25890_charger.c struct bq25890_lookup lt; lt 285 drivers/power/supply/bq25890_charger.c [TBL_TREG] = { .lt = {bq25890_treg_tbl, BQ25890_TREG_TBL_SIZE} }, lt 286 drivers/power/supply/bq25890_charger.c [TBL_BOOSTI] = { .lt = {bq25890_boosti_tbl, BQ25890_BOOSTI_TBL_SIZE} } lt 313 drivers/power/supply/bq25890_charger.c const u32 *tbl = bq25890_tables[id].lt.tbl; lt 314 drivers/power/supply/bq25890_charger.c u32 tbl_size = bq25890_tables[id].lt.size; lt 339 drivers/power/supply/bq25890_charger.c return bq25890_tables[id].lt.tbl[idx]; lt 711 drivers/scsi/be2iscsi/be_main.h u8 lt; /* DWORD 0 */ lt 779 drivers/scsi/be2iscsi/be_main.h u8 lt; /* DWORD 11 */ lt 867 drivers/scsi/be2iscsi/be_main.h u8 lt; /* DWORD 0 */ lt 202 kernel/locking/lockdep.c static void lock_time_inc(struct lock_time *lt, u64 time) lt 204 kernel/locking/lockdep.c if (time > lt->max) lt 205 kernel/locking/lockdep.c lt->max = time; lt 207 kernel/locking/lockdep.c if (time < lt->min || !lt->nr) lt 208 kernel/locking/lockdep.c lt->min = time; lt 210 kernel/locking/lockdep.c lt->total += time; lt 211 kernel/locking/lockdep.c lt->nr++; lt 397 kernel/locking/lockdep_proc.c static void seq_lock_time(struct seq_file *m, struct lock_time *lt) lt 399 kernel/locking/lockdep_proc.c seq_printf(m, "%14lu", lt->nr); lt 400 kernel/locking/lockdep_proc.c seq_time(m, lt->min); lt 401 kernel/locking/lockdep_proc.c seq_time(m, lt->max); lt 402 kernel/locking/lockdep_proc.c seq_time(m, lt->total); lt 403 kernel/locking/lockdep_proc.c seq_time(m, lt->nr ? div_s64(lt->total, lt->nr) : 0); lt 1739 net/ipv4/fib_trie.c struct trie *lt; lt 1749 net/ipv4/fib_trie.c lt = (struct trie *)local_tb->tb_data; lt 1769 net/ipv4/fib_trie.c local_l = fib_find_node(lt, &local_tp, l->key); lt 1771 net/ipv4/fib_trie.c if (fib_insert_alias(lt, local_tp, local_l, new_fa, lt 479 net/netfilter/ipset/ip_set_hash_gen.h struct list_head *l, *lt; lt 485 net/netfilter/ipset/ip_set_hash_gen.h list_for_each_safe(l, lt, &h->ad) { lt 655 net/netfilter/ipset/ip_set_hash_gen.h struct list_head *l, *lt; lt 790 net/netfilter/ipset/ip_set_hash_gen.h list_for_each_safe(l, lt, &h->ad) { lt 521 net/xfrm/xfrm_user.c struct nlattr *lt = attrs[XFRMA_LTIME_VAL]; lt 541 net/xfrm/xfrm_user.c if (lt) { lt 543 net/xfrm/xfrm_user.c ltime = nla_data(lt); lt 2092 net/xfrm/xfrm_user.c struct nlattr *lt = attrs[XFRMA_LTIME_VAL]; lt 2096 net/xfrm/xfrm_user.c if (!lt && !rp && !re && !et && !rt) lt 831 scripts/unifdef.c Linetype lt; lt 837 scripts/unifdef.c lt = eval_unary(ops, valp, &cp); lt 838 scripts/unifdef.c if (lt == LT_ERROR) lt 840 scripts/unifdef.c if (lt != LT_IF) { lt 842 scripts/unifdef.c lt = *valp ? LT_TRUE : LT_FALSE; lt 847 scripts/unifdef.c lt = eval_table(eval_ops, valp, &cp); lt 848 scripts/unifdef.c if (lt == LT_ERROR) lt 858 scripts/unifdef.c lt = *valp ? LT_TRUE : LT_FALSE; lt 871 scripts/unifdef.c lt = LT_IF; lt 874 scripts/unifdef.c lt = *valp ? LT_TRUE : LT_FALSE; lt 886 scripts/unifdef.c lt = LT_IF; lt 890 scripts/unifdef.c lt = LT_FALSE; lt 895 scripts/unifdef.c lt = *valp ? LT_TRUE : LT_FALSE; lt 906 scripts/unifdef.c return (lt); lt 918 scripts/unifdef.c Linetype lt, rt; lt 922 scripts/unifdef.c lt = ops->inner(ops+1, valp, &cp); lt 923 scripts/unifdef.c if (lt == LT_ERROR) lt 937 scripts/unifdef.c lt = op->fn(valp, lt, *valp, rt, val); lt 942 scripts/unifdef.c debug("eval%d lt = %s", ops - eval_ops, linetype_name[lt]); lt 943 scripts/unifdef.c return (lt);