MCIF_WB_BUF_3_ADDR_Y_OFFSET   71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB_BUF_3_ADDR_Y_OFFSET  127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
MCIF_WB_BUF_3_ADDR_Y_OFFSET  192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
MCIF_WB_BUF_3_ADDR_Y_OFFSET  234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
MCIF_WB_BUF_3_ADDR_Y_OFFSET  113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0);
MCIF_WB_BUF_3_ADDR_Y_OFFSET   85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB_BUF_3_ADDR_Y_OFFSET  231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
MCIF_WB_BUF_3_ADDR_Y_OFFSET  393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
MCIF_WB_BUF_3_ADDR_Y_OFFSET  467 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\