MCIF_WB_BUF_3_ADDR_C_OFFSET   73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB_BUF_3_ADDR_C_OFFSET  129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
MCIF_WB_BUF_3_ADDR_C_OFFSET  194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
MCIF_WB_BUF_3_ADDR_C_OFFSET  236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
MCIF_WB_BUF_3_ADDR_C_OFFSET  119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0);
MCIF_WB_BUF_3_ADDR_C_OFFSET   87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB_BUF_3_ADDR_C_OFFSET  233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
MCIF_WB_BUF_3_ADDR_C_OFFSET  395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
MCIF_WB_BUF_3_ADDR_C_OFFSET  469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\