lro_en 1044 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en) lro_en 1046 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en); lro_en 508 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en); lro_en 305 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hw_ioctxt.lro_en = 1; lro_en 152 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h u8 lro_en; lro_en 553 drivers/net/ethernet/huawei/hinic/hinic_port.c int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en, lro_en 564 drivers/net/ethernet/huawei/hinic/hinic_port.c ipv4_en = lro_en ? 1 : 0; lro_en 565 drivers/net/ethernet/huawei/hinic/hinic_port.c ipv6_en = lro_en ? 1 : 0; lro_en 543 drivers/net/ethernet/huawei/hinic/hinic_port.h int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en, lro_en 260 drivers/net/ethernet/mellanox/mlx5/core/en.h bool lro_en; lro_en 84 drivers/net/ethernet/mellanox/mlx5/core/en/params.c return !params->lro_en && linear_frag_sz <= PAGE_SIZE; lro_en 1828 drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c } else if (priv->channels.params.lro_en) { lro_en 2696 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (!params->lro_en) lro_en 3686 drivers/net/ethernet/mellanox/mlx5/core/en_main.c new_channels.params.lro_en = enable; lro_en 3931 drivers/net/ethernet/mellanox/mlx5/core/en_main.c reset = !params->lro_en; lro_en 4388 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (priv->channels.params.lro_en) { lro_en 4834 drivers/net/ethernet/mellanox/mlx5/core/en_main.c params->lro_en = !slow_pci_heuristic(mdev); lro_en 4965 drivers/net/ethernet/mellanox/mlx5/core/en_main.c if (!priv->channels.params.lro_en) lro_en 69 drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c params->lro_en = false;