lrc_reg_state 59 drivers/gpu/drm/i915/gt/intel_context_types.h u32 *lrc_reg_state; lrc_reg_state 670 drivers/gpu/drm/i915/gt/intel_lrc.c prev = ce->lrc_reg_state[CTX_RING_TAIL + 1]; lrc_reg_state 673 drivers/gpu/drm/i915/gt/intel_lrc.c ce->lrc_reg_state[CTX_RING_TAIL + 1] = tail; lrc_reg_state 1217 drivers/gpu/drm/i915/gt/intel_lrc.c u32 *regs = ve->context.lrc_reg_state; lrc_reg_state 1754 drivers/gpu/drm/i915/gt/intel_lrc.c check_redzone((void *)ce->lrc_reg_state - LRC_STATE_PN * PAGE_SIZE, lrc_reg_state 1767 drivers/gpu/drm/i915/gt/intel_lrc.c u32 *regs = ce->lrc_reg_state; lrc_reg_state 1812 drivers/gpu/drm/i915/gt/intel_lrc.c ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; lrc_reg_state 2529 drivers/gpu/drm/i915/gt/intel_lrc.c regs = ce->lrc_reg_state; lrc_reg_state 3475 drivers/gpu/drm/i915/gt/intel_lrc.c virtual_update_register_offsets(ve->context.lrc_reg_state, lrc_reg_state 4011 drivers/gpu/drm/i915/gt/intel_lrc.c u32 *regs = ce->lrc_reg_state; lrc_reg_state 882 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c u32 sr = ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1]; lrc_reg_state 458 drivers/gpu/drm/i915/gvt/mmio_context.c const u32 *reg_state = ce->lrc_reg_state; lrc_reg_state 536 drivers/gpu/drm/i915/gvt/scheduler.c (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;