MCIF_WB_BUF_1_ADDR_Y   62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
MCIF_WB_BUF_1_ADDR_Y  118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
MCIF_WB_BUF_1_ADDR_Y  183 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type MCIF_WB_BUF_1_ADDR_Y;\
MCIF_WB_BUF_1_ADDR_Y  225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t MCIF_WB_BUF_1_ADDR_Y;
MCIF_WB_BUF_1_ADDR_Y   86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
MCIF_WB_BUF_1_ADDR_Y   76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
MCIF_WB_BUF_1_ADDR_Y  222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
MCIF_WB_BUF_1_ADDR_Y  384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	type MCIF_WB_BUF_1_ADDR_Y;\
MCIF_WB_BUF_1_ADDR_Y  458 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	uint32_t MCIF_WB_BUF_1_ADDR_Y;\