MCIF_WB_BUFMGR_VCE_CONTROL   78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
MCIF_WB_BUFMGR_VCE_CONTROL  241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
MCIF_WB_BUFMGR_VCE_CONTROL  199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);
MCIF_WB_BUFMGR_VCE_CONTROL  217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN,  params->vce_int_en);
MCIF_WB_BUFMGR_VCE_CONTROL  218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN,  params->vce_slice_int_en);
MCIF_WB_BUFMGR_VCE_CONTROL   92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
MCIF_WB_BUFMGR_VCE_CONTROL  474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\