MCIF_WB_BUFMGR_SW_LOCK  109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
MCIF_WB_BUFMGR_SW_LOCK  174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	type MCIF_WB_BUFMGR_SW_LOCK;\
MCIF_WB_BUFMGR_SW_LOCK   83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);
MCIF_WB_BUFMGR_SW_LOCK  284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);
MCIF_WB_BUFMGR_SW_LOCK  289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);
MCIF_WB_BUFMGR_SW_LOCK  123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
MCIF_WB_BUFMGR_SW_LOCK  285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	type MCIF_WB_BUFMGR_SW_LOCK;\