lpr0 410 arch/arm/mach-at91/pm.c u32 lpr0, lpr1 = 0; lpr0 435 arch/arm/mach-at91/pm.c lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; lpr0 436 arch/arm/mach-at91/pm.c lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; lpr0 439 arch/arm/mach-at91/pm.c at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); lpr0 455 arch/arm/mach-at91/pm.c u32 lpr0; lpr0 459 arch/arm/mach-at91/pm.c lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; lpr0 460 arch/arm/mach-at91/pm.c lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; lpr0 462 arch/arm/mach-at91/pm.c at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); lpr0 474 arch/arm/mach-at91/pm.c u32 lpr0, lpr1 = 0; lpr0 484 arch/arm/mach-at91/pm.c lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; lpr0 485 arch/arm/mach-at91/pm.c lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; lpr0 488 arch/arm/mach-at91/pm.c at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);