MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL  125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\