MCIF_WB            58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
MCIF_WB            59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
MCIF_WB            60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
MCIF_WB            61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
MCIF_WB            62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
MCIF_WB            65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
MCIF_WB            69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
MCIF_WB            73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
MCIF_WB            77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
MCIF_WB            79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
MCIF_WB            80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
MCIF_WB            81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
MCIF_WB            82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
MCIF_WB            83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
MCIF_WB            84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
MCIF_WB            60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
MCIF_WB            61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
MCIF_WB            62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
MCIF_WB            63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
MCIF_WB            64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
MCIF_WB            65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
MCIF_WB            66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
MCIF_WB            67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
MCIF_WB            68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
MCIF_WB            69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
MCIF_WB            70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
MCIF_WB            71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\
MCIF_WB            72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
MCIF_WB            73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
MCIF_WB            74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\
MCIF_WB            75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\
MCIF_WB            76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
MCIF_WB            79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
MCIF_WB            83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
MCIF_WB            87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
MCIF_WB            89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
MCIF_WB            90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
MCIF_WB            91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
MCIF_WB            92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
MCIF_WB            93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
MCIF_WB            94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
MCIF_WB            95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
MCIF_WB            96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\
MCIF_WB            97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
MCIF_WB            98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\
MCIF_WB            99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\
MCIF_WB           100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\
MCIF_WB           101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
MCIF_WB           102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
MCIF_WB           103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\
MCIF_WB           104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\
MCIF_WB           105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\
MCIF_WB           106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\
MCIF_WB           107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\
MCIF_WB           108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\
MCIF_WB           109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\
MCIF_WB           110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\
MCIF_WB           111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\
MCIF_WB           112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\
MCIF_WB           113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\
MCIF_WB           114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\