lower_pipe 59 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c u32 lower_pipe = 0; lower_pipe 68 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c lower_pipe = FLD_SPLIT_DISPLAY_CMD; lower_pipe 71 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c lower_pipe |= FLD_INTF_1_SW_TRG_MUX; lower_pipe 73 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c lower_pipe |= FLD_INTF_2_SW_TRG_MUX; lower_pipe 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c upper_pipe = lower_pipe; lower_pipe 77 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c lower_pipe = FLD_INTF_1_SW_TRG_MUX; lower_pipe 80 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c lower_pipe = FLD_INTF_2_SW_TRG_MUX; lower_pipe 87 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);