MASTER_COMM_INTERRUPT 66 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 78 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 80 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 219 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, MASTER_COMM_INTERRUPT 234 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 247 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, MASTER_COMM_INTERRUPT 320 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 329 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 99 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ MASTER_COMM_INTERRUPT 189 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h type MASTER_COMM_INTERRUPT; \ MASTER_COMM_INTERRUPT 129 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 142 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 223 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 265 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 300 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 311 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 354 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_INTERRUPT 364 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 367 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_INTERRUPT 389 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_INTERRUPT 402 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 405 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_INTERRUPT 466 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_INTERRUPT 473 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 476 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_INTERRUPT 525 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 538 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 635 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_INTERRUPT 679 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 682 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 700 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 711 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 743 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 749 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 752 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 766 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 772 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_INTERRUPT 775 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_INTERRUPT 92 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ MASTER_COMM_INTERRUPT 118 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ MASTER_COMM_INTERRUPT 140 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h type MASTER_COMM_INTERRUPT; \