MASTER_COMM_DATA_REG1 70 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); MASTER_COMM_DATA_REG1 228 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); MASTER_COMM_DATA_REG1 40 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(MASTER_COMM_DATA_REG1) MASTER_COMM_DATA_REG1 224 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t MASTER_COMM_DATA_REG1; MASTER_COMM_DATA_REG1 240 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), MASTER_COMM_DATA_REG1 305 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); MASTER_COMM_DATA_REG1 357 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); MASTER_COMM_DATA_REG1 392 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); MASTER_COMM_DATA_REG1 653 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), MASTER_COMM_DATA_REG1 705 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); MASTER_COMM_DATA_REG1 38 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG1), \ MASTER_COMM_DATA_REG1 55 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_DATA_REG1), \ MASTER_COMM_DATA_REG1 168 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_DATA_REG1; MASTER_COMM_DATA_REG1 118 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_DATA_REG1;