MASTER_COMM_CNTL_REG 66 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 78 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 80 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 219 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, MASTER_COMM_CNTL_REG 234 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 247 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, MASTER_COMM_CNTL_REG 320 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 329 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 38 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h SR(MASTER_COMM_CNTL_REG), \ MASTER_COMM_CNTL_REG 99 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ MASTER_COMM_CNTL_REG 222 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h uint32_t MASTER_COMM_CNTL_REG; MASTER_COMM_CNTL_REG 129 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 142 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 223 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 265 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 300 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 311 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 354 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_CNTL_REG 364 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 367 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_CNTL_REG 389 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_CNTL_REG 402 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 405 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_CNTL_REG 466 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_CNTL_REG 473 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 476 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); MASTER_COMM_CNTL_REG 525 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 538 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 635 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, MASTER_COMM_CNTL_REG 679 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 682 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 700 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 711 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 743 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 749 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 752 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 766 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 772 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); MASTER_COMM_CNTL_REG 775 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); MASTER_COMM_CNTL_REG 42 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_CNTL_REG), \ MASTER_COMM_CNTL_REG 59 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h SR(MASTER_COMM_CNTL_REG), \ MASTER_COMM_CNTL_REG 92 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ MASTER_COMM_CNTL_REG 118 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ MASTER_COMM_CNTL_REG 172 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h uint32_t MASTER_COMM_CNTL_REG; MASTER_COMM_CNTL_REG 122 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t MASTER_COMM_CNTL_REG;