MASTER_COMM_CMD_REG_BYTE0 74 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET, MASTER_COMM_CMD_REG_BYTE0 231 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); MASTER_COMM_CMD_REG_BYTE0 325 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET, MASTER_COMM_CMD_REG_BYTE0 100 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ MASTER_COMM_CMD_REG_BYTE0 190 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h type MASTER_COMM_CMD_REG_BYTE0; \ MASTER_COMM_CMD_REG_BYTE0 135 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 138 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 262 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c MASTER_COMM_CMD_REG_BYTE0, PSR_SET); MASTER_COMM_CMD_REG_BYTE0 308 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); MASTER_COMM_CMD_REG_BYTE0 360 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 398 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 469 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 531 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 534 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MASTER_COMM_CMD_REG_BYTE0 676 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c MASTER_COMM_CMD_REG_BYTE0, PSR_SET); MASTER_COMM_CMD_REG_BYTE0 708 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); MASTER_COMM_CMD_REG_BYTE0 746 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK); MASTER_COMM_CMD_REG_BYTE0 769 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK); MASTER_COMM_CMD_REG_BYTE0 91 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ MASTER_COMM_CMD_REG_BYTE0 117 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ MASTER_COMM_CMD_REG_BYTE0 139 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h type MASTER_COMM_CMD_REG_BYTE0; \