MASTER_COMM_CMD_REG   73 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE_2(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG  231 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
MASTER_COMM_CMD_REG  324 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE_2(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG   39 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SR(MASTER_COMM_CMD_REG), \
MASTER_COMM_CMD_REG  100 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
MASTER_COMM_CMD_REG  101 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
MASTER_COMM_CMD_REG  102 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
MASTER_COMM_CMD_REG  223 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	uint32_t MASTER_COMM_CMD_REG;
MASTER_COMM_CMD_REG  135 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  138 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  261 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG  308 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
MASTER_COMM_CMD_REG  360 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  398 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  469 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  531 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  534 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
MASTER_COMM_CMD_REG  675 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG,
MASTER_COMM_CMD_REG  708 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
MASTER_COMM_CMD_REG  746 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
MASTER_COMM_CMD_REG  769 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
MASTER_COMM_CMD_REG   41 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	SR(MASTER_COMM_CMD_REG), \
MASTER_COMM_CMD_REG   58 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	SR(MASTER_COMM_CMD_REG), \
MASTER_COMM_CMD_REG   90 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(MASTER_COMM_CMD_REG, \
MASTER_COMM_CMD_REG  116 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	DMCU_SF(MASTER_COMM_CMD_REG, \
MASTER_COMM_CMD_REG  171 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	uint32_t MASTER_COMM_CMD_REG;
MASTER_COMM_CMD_REG  121 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 	uint32_t MASTER_COMM_CMD_REG;