MASK_reg           30 drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h 	uint32_t MASK_reg;
MASK_reg           87 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 	regval = REG_GET_3(gpio.MASK_reg,
MASK_reg          101 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 				REG_SET_2(gpio.MASK_reg, regval,
MASK_reg          114 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 			reg2 = REG_GET_2(gpio.MASK_reg,
MASK_reg          119 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 				REG_SET(gpio.MASK_reg, regval,
MASK_reg          128 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 				REG_SET(gpio.MASK_reg, regval,
MASK_reg          149 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 			REG_UPDATE(gpio.MASK_reg,
MASK_reg          166 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 			REG_SET(gpio.MASK_reg, regval,
MASK_reg           45 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 	REG_GET(MASK_reg, MASK, &gpio->store.mask);
MASK_reg           54 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 	REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
MASK_reg          152 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 1);
MASK_reg          158 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 1);
MASK_reg          164 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 1);
MASK_reg          168 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 0);
MASK_reg          172 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c 		REG_UPDATE(MASK_reg, MASK, 0);