MAILBOX_CONTROL 321 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); MAILBOX_CONTROL 324 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1); MAILBOX_CONTROL 346 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, MAILBOX_CONTROL 368 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); MAILBOX_CONTROL 390 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK);