loaded_bb        3277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
loaded_bb        3419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
loaded_bb        3421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			cap_soc_clocks(loaded_bb, max_clocks);
loaded_bb        3426 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	patch_bounding_box(dc, loaded_bb);
loaded_bb        3439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
loaded_bb        3568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
loaded_bb        3576 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (loaded_bb->num_states == 1) {
loaded_bb        3584 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		} else if (loaded_bb->num_states > 1) {
loaded_bb        3585 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
loaded_bb        3589 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
loaded_bb        3590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;