lnkbase           114 arch/mips/pci/msi-xlp.c 	uint64_t	lnkbase;
lnkbase           142 arch/mips/pci/msi-xlp.c 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
lnkbase           145 arch/mips/pci/msi-xlp.c 		nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
lnkbase           159 arch/mips/pci/msi-xlp.c 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
lnkbase           162 arch/mips/pci/msi-xlp.c 		nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
lnkbase           177 arch/mips/pci/msi-xlp.c 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);
lnkbase           179 arch/mips/pci/msi-xlp.c 		nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
lnkbase           224 arch/mips/pci/msi-xlp.c 	nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
lnkbase           248 arch/mips/pci/msi-xlp.c static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
lnkbase           253 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
lnkbase           256 arch/mips/pci/msi-xlp.c 			nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
lnkbase           259 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
lnkbase           262 arch/mips/pci/msi-xlp.c 			nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
lnkbase           266 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, 0x1);	/* CMD */
lnkbase           269 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, 0x1, val);
lnkbase           273 arch/mips/pci/msi-xlp.c 	val = nlm_read_pci_reg(lnkbase, 0xf);
lnkbase           276 arch/mips/pci/msi-xlp.c 	nlm_write_pci_reg(lnkbase, 0xf, val);
lnkbase           279 arch/mips/pci/msi-xlp.c 	nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
lnkbase           280 arch/mips/pci/msi-xlp.c 	nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
lnkbase           283 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
lnkbase           286 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
lnkbase           293 arch/mips/pci/msi-xlp.c static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
lnkbase           310 arch/mips/pci/msi-xlp.c 		xlp_config_link_msi(lnkbase, lirq, msiaddr);
lnkbase           346 arch/mips/pci/msi-xlp.c static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
lnkbase           350 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, 0x2C);
lnkbase           353 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, 0x2C, val);
lnkbase           357 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
lnkbase           360 arch/mips/pci/msi-xlp.c 			nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
lnkbase           363 arch/mips/pci/msi-xlp.c 		val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
lnkbase           366 arch/mips/pci/msi-xlp.c 			nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
lnkbase           370 arch/mips/pci/msi-xlp.c 	val = nlm_read_reg(lnkbase, 0x1);	/* CMD */
lnkbase           373 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, 0x1, val);
lnkbase           377 arch/mips/pci/msi-xlp.c 	val = nlm_read_pci_reg(lnkbase, 0xf);
lnkbase           380 arch/mips/pci/msi-xlp.c 	nlm_write_pci_reg(lnkbase, 0xf, val);
lnkbase           384 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,
lnkbase           386 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,
lnkbase           390 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,
lnkbase           392 arch/mips/pci/msi-xlp.c 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
lnkbase           400 arch/mips/pci/msi-xlp.c static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
lnkbase           418 arch/mips/pci/msi-xlp.c 		xlp_config_link_msix(lnkbase, lirq, msixaddr);
lnkbase           447 arch/mips/pci/msi-xlp.c 	uint64_t lnkbase;
lnkbase           458 arch/mips/pci/msi-xlp.c 	lnkbase = nlm_get_pcie_base(node, link);
lnkbase           461 arch/mips/pci/msi-xlp.c 		return xlp_setup_msix(lnkbase, node, link, desc);
lnkbase           463 arch/mips/pci/msi-xlp.c 		return xlp_setup_msi(lnkbase, node, link, desc);
lnkbase           482 arch/mips/pci/msi-xlp.c 	md->lnkbase = nlm_get_pcie_base(node, link);
lnkbase           495 arch/mips/pci/msi-xlp.c 			nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i +
lnkbase           525 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
lnkbase           528 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
lnkbase           555 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
lnkbase           557 arch/mips/pci/msi-xlp.c 		status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
lnkbase           241 arch/mips/pci/pci-xlp.c 	uint64_t nbubase, lnkbase;
lnkbase           245 arch/mips/pci/pci-xlp.c 	lnkbase = nlm_get_pcie_base(node, link);
lnkbase           254 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
lnkbase           258 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase,
lnkbase           263 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
lnkbase           267 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase,
lnkbase           271 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
lnkbase           275 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
lnkbase           278 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
lnkbase           281 arch/mips/pci/pci-xlp.c 		nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);