ln0 3064 drivers/gpu/drm/i915/display/intel_ddi.c u32 ln0, ln1, lane_mask; ln0 3069 drivers/gpu/drm/i915/display/intel_ddi.c ln0 = I915_READ(MG_DP_MODE(0, port)); ln0 3074 drivers/gpu/drm/i915/display/intel_ddi.c ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); ln0 3084 drivers/gpu/drm/i915/display/intel_ddi.c ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; ln0 3087 drivers/gpu/drm/i915/display/intel_ddi.c ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | ln0 3098 drivers/gpu/drm/i915/display/intel_ddi.c ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | ln0 3109 drivers/gpu/drm/i915/display/intel_ddi.c ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE; ln0 3118 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(MG_DP_MODE(0, port), ln0);