lm_idx             93 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	int lm_idx, lm_horiz_position;
lm_idx             99 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
lm_idx            100 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
lm_idx            101 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
lm_idx            128 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	uint32_t stage_idx, lm_idx;
lm_idx            167 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
lm_idx            168 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
lm_idx            171 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			mixer[lm_idx].flush_mask |= flush_mask;
lm_idx            174 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 				mixer[lm_idx].mixer_op_mode = 0;
lm_idx            176 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 				mixer[lm_idx].mixer_op_mode |=