LinkLevel         273 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     SMU71_Discrete_LinkLevel             LinkLevel               [SMU71_MAX_LEVELS_LINK];
LinkLevel         268 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	SMU72_Discrete_LinkLevel            LinkLevel[SMU72_MAX_LEVELS_LINK];
LinkLevel         252 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h     SMU73_Discrete_LinkLevel            LinkLevel               [SMU73_MAX_LEVELS_LINK];
LinkLevel         284 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	SMU74_Discrete_LinkLevel            LinkLevel[SMU74_MAX_LEVELS_LINK];
LinkLevel         290 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	SMU75_Discrete_LinkLevel            LinkLevel               [SMU75_MAX_LEVELS_LINK];
LinkLevel         326 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];
LinkLevel        1004 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->LinkLevel[i].PcieGenSpeed  =
LinkLevel        1006 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->LinkLevel[i].PcieLaneCount =
LinkLevel        1008 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->LinkLevel[i].EnabledForActivity = 1;
LinkLevel        1009 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
LinkLevel        1010 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
LinkLevel         839 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].PcieGenSpeed  =
LinkLevel         841 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
LinkLevel         843 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].EnabledForActivity = 1;
LinkLevel         844 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
LinkLevel         845 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
LinkLevel         846 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
LinkLevel         773 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].PcieGenSpeed  =
LinkLevel         775 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].PcieLaneCount =
LinkLevel         777 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].EnabledForActivity =
LinkLevel         779 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].SPC =
LinkLevel         781 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].DownThreshold =
LinkLevel         783 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		table->LinkLevel[i].UpThreshold =
LinkLevel         777 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].PcieGenSpeed  =
LinkLevel         779 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
LinkLevel         781 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].EnabledForActivity = 1;
LinkLevel         782 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
LinkLevel         783 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
LinkLevel         784 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
LinkLevel        1995 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
LinkLevel         516 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].PcieGenSpeed  =
LinkLevel         518 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].PcieLaneCount =
LinkLevel         520 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].EnabledForActivity =
LinkLevel         522 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].SPC =
LinkLevel         524 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].DownThreshold =
LinkLevel         526 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->LinkLevel[i].UpThreshold =
LinkLevel         579 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].PcieGenSpeed  =
LinkLevel         581 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
LinkLevel         583 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].EnabledForActivity = 1;
LinkLevel         584 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
LinkLevel         585 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
LinkLevel         586 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
LinkLevel        2120 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			table->LinkLevel[i - 1].BifSclkDfs =
LinkLevel        2634 drivers/gpu/drm/radeon/ci_dpm.c 		table->LinkLevel[i].PcieGenSpeed =
LinkLevel        2636 drivers/gpu/drm/radeon/ci_dpm.c 		table->LinkLevel[i].PcieLaneCount =
LinkLevel        2638 drivers/gpu/drm/radeon/ci_dpm.c 		table->LinkLevel[i].EnabledForActivity = 1;
LinkLevel        2639 drivers/gpu/drm/radeon/ci_dpm.c 		table->LinkLevel[i].DownT = cpu_to_be32(5);
LinkLevel        2640 drivers/gpu/drm/radeon/ci_dpm.c 		table->LinkLevel[i].UpT = cpu_to_be32(30);
LinkLevel         325 drivers/gpu/drm/radeon/smu7_discrete.h     SMU7_Discrete_LinkLevel             LinkLevel               [SMU7_MAX_LEVELS_LINK];