link_width_cntl 1276 drivers/gpu/drm/amd/amdgpu/si.c u32 link_width_cntl; link_width_cntl 1281 drivers/gpu/drm/amd/amdgpu/si.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 1283 drivers/gpu/drm/amd/amdgpu/si.c switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { link_width_cntl 1301 drivers/gpu/drm/amd/amdgpu/si.c u32 link_width_cntl, mask; link_width_cntl 1330 drivers/gpu/drm/amd/amdgpu/si.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 1331 drivers/gpu/drm/amd/amdgpu/si.c link_width_cntl &= ~LC_LINK_WIDTH_MASK; link_width_cntl 1332 drivers/gpu/drm/amd/amdgpu/si.c link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; link_width_cntl 1333 drivers/gpu/drm/amd/amdgpu/si.c link_width_cntl |= (LC_RECONFIG_NOW | link_width_cntl 1336 drivers/gpu/drm/amd/amdgpu/si.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 5327 drivers/gpu/drm/radeon/evergreen.c u32 link_width_cntl, speed_cntl; link_width_cntl 5357 drivers/gpu/drm/radeon/evergreen.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 5358 drivers/gpu/drm/radeon/evergreen.c link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl 5359 drivers/gpu/drm/radeon/evergreen.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 5378 drivers/gpu/drm/radeon/evergreen.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 5381 drivers/gpu/drm/radeon/evergreen.c link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl 5383 drivers/gpu/drm/radeon/evergreen.c link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl 5384 drivers/gpu/drm/radeon/evergreen.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 504 drivers/gpu/drm/radeon/r300.c uint32_t link_width_cntl, mask; link_width_cntl 539 drivers/gpu/drm/radeon/r300.c link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 541 drivers/gpu/drm/radeon/r300.c if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == link_width_cntl 545 drivers/gpu/drm/radeon/r300.c link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | link_width_cntl 549 drivers/gpu/drm/radeon/r300.c link_width_cntl |= mask; link_width_cntl 550 drivers/gpu/drm/radeon/r300.c WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 551 drivers/gpu/drm/radeon/r300.c WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | link_width_cntl 555 drivers/gpu/drm/radeon/r300.c link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 556 drivers/gpu/drm/radeon/r300.c while (link_width_cntl == 0xffffffff) link_width_cntl 557 drivers/gpu/drm/radeon/r300.c link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 563 drivers/gpu/drm/radeon/r300.c u32 link_width_cntl; link_width_cntl 573 drivers/gpu/drm/radeon/r300.c link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 575 drivers/gpu/drm/radeon/r300.c switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { link_width_cntl 4403 drivers/gpu/drm/radeon/r600.c u32 link_width_cntl, mask; link_width_cntl 4445 drivers/gpu/drm/radeon/r600.c link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 4446 drivers/gpu/drm/radeon/r600.c link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; link_width_cntl 4447 drivers/gpu/drm/radeon/r600.c link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; link_width_cntl 4448 drivers/gpu/drm/radeon/r600.c link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | link_width_cntl 4451 drivers/gpu/drm/radeon/r600.c WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 4456 drivers/gpu/drm/radeon/r600.c u32 link_width_cntl; link_width_cntl 4470 drivers/gpu/drm/radeon/r600.c link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 4472 drivers/gpu/drm/radeon/r600.c switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { link_width_cntl 4493 drivers/gpu/drm/radeon/r600.c u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; link_width_cntl 4530 drivers/gpu/drm/radeon/r600.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 4531 drivers/gpu/drm/radeon/r600.c link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl 4532 drivers/gpu/drm/radeon/r600.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 4533 drivers/gpu/drm/radeon/r600.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 4534 drivers/gpu/drm/radeon/r600.c if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { link_width_cntl 4535 drivers/gpu/drm/radeon/r600.c lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; link_width_cntl 4536 drivers/gpu/drm/radeon/r600.c link_width_cntl &= ~(LC_LINK_WIDTH_MASK | link_width_cntl 4538 drivers/gpu/drm/radeon/r600.c link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; link_width_cntl 4539 drivers/gpu/drm/radeon/r600.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 4541 drivers/gpu/drm/radeon/r600.c link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl 4542 drivers/gpu/drm/radeon/r600.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 4595 drivers/gpu/drm/radeon/r600.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 4598 drivers/gpu/drm/radeon/r600.c link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl 4600 drivers/gpu/drm/radeon/r600.c link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl 4601 drivers/gpu/drm/radeon/r600.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 2027 drivers/gpu/drm/radeon/rv770.c u32 link_width_cntl, lanes, speed_cntl, tmp; link_width_cntl 2050 drivers/gpu/drm/radeon/rv770.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 2051 drivers/gpu/drm/radeon/rv770.c link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl 2052 drivers/gpu/drm/radeon/rv770.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 2053 drivers/gpu/drm/radeon/rv770.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 2054 drivers/gpu/drm/radeon/rv770.c if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { link_width_cntl 2055 drivers/gpu/drm/radeon/rv770.c lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; link_width_cntl 2056 drivers/gpu/drm/radeon/rv770.c link_width_cntl &= ~(LC_LINK_WIDTH_MASK | link_width_cntl 2058 drivers/gpu/drm/radeon/rv770.c link_width_cntl |= lanes | LC_RECONFIG_NOW | link_width_cntl 2060 drivers/gpu/drm/radeon/rv770.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 2062 drivers/gpu/drm/radeon/rv770.c link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl 2063 drivers/gpu/drm/radeon/rv770.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); link_width_cntl 2096 drivers/gpu/drm/radeon/rv770.c link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); link_width_cntl 2099 drivers/gpu/drm/radeon/rv770.c link_width_cntl |= LC_UPCONFIGURE_DIS; link_width_cntl 2101 drivers/gpu/drm/radeon/rv770.c link_width_cntl &= ~LC_UPCONFIGURE_DIS; link_width_cntl 2102 drivers/gpu/drm/radeon/rv770.c WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);