link_training_setting 400 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c const struct link_training_settings *link_training_setting, link_training_setting 407 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting-> link_training_setting 410 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting-> link_training_setting 416 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 1; lane < link_training_setting->link_settings.lane_count; link_training_setting 418 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link_training_setting->lane_settings[lane].VOLTAGE_SWING > link_training_setting 422 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting-> link_training_setting 425 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link_training_setting->lane_settings[lane].PRE_EMPHASIS > link_training_setting 428 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting-> link_training_setting 473 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.link_rate; link_training_setting 475 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count; link_training_setting 477 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.link_spread; link_training_setting 480 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count; link_training_setting 495 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c const struct link_training_settings *link_training_setting, link_training_setting 514 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting->link_settings.lane_count); link_training_setting 539 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count; link_training_setting 541 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.link_rate; link_training_setting 543 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.link_spread; link_training_setting 546 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting->link_settings.lane_count); link_training_setting 574 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c const struct link_training_settings *link_training_setting) link_training_setting 580 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting-> link_training_setting 584 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint8_t)(link_training_setting-> link_training_setting 587 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint8_t)(link_training_setting-> link_training_setting 590 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (link_training_setting-> link_training_setting 594 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (link_training_setting-> link_training_setting 602 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count); link_training_setting 631 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->cur_lane_setting = link_training_setting->lane_settings[0];