link_bw 1915 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t link_bw; link_bw 1923 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_bw = dc_link_bandwidth_kbps( link_bw 1926 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (req_bw <= link_bw) { link_bw 1952 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t link_bw; link_bw 1974 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_bw = dc_link_bandwidth_kbps( link_bw 1977 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (req_bw <= link_bw) { link_bw 160 drivers/gpu/drm/drm_dp_helper.c int drm_dp_bw_code_to_link_rate(u8 link_bw) link_bw 163 drivers/gpu/drm/drm_dp_helper.c return link_bw * 27000; link_bw 264 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t link_bw; link_bw 359 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_dp_link_clock(uint8_t link_bw) link_bw 361 drivers/gpu/drm/gma500/cdv_intel_dp.c if (link_bw == DP_LINK_BW_2_7) link_bw 919 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_bw = bws[clock]; link_bw 921 drivers/gpu/drm/gma500/cdv_intel_dp.c adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); link_bw 924 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_bw, intel_dp->lane_count, link_bw 933 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_bw = bws[max_clock]; link_bw 934 drivers/gpu/drm/gma500/cdv_intel_dp.c adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); link_bw 937 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_bw, intel_dp->lane_count, link_bw 1073 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_configuration[0] = intel_dp->link_bw; link_bw 7259 drivers/gpu/drm/i915/display/intel_display.c int lane, link_bw, fdi_dotclock, ret; link_bw 7270 drivers/gpu/drm/i915/display/intel_display.c link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); link_bw 7274 drivers/gpu/drm/i915/display/intel_display.c lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, link_bw 7280 drivers/gpu/drm/i915/display/intel_display.c link_bw, &pipe_config->fdi_m_n, false, false); link_bw 9515 drivers/gpu/drm/i915/display/intel_display.c int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) link_bw 9523 drivers/gpu/drm/i915/display/intel_display.c return DIV_ROUND_UP(bps, link_bw * 8); link_bw 462 drivers/gpu/drm/i915/display/intel_display.h int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); link_bw 1819 drivers/gpu/drm/i915/display/intel_dp.c u8 *link_bw, u8 *rate_select) link_bw 1823 drivers/gpu/drm/i915/display/intel_dp.c *link_bw = 0; link_bw 1827 drivers/gpu/drm/i915/display/intel_dp.c *link_bw = drm_dp_link_rate_to_bw_code(port_clock); link_bw 100 drivers/gpu/drm/i915/display/intel_dp.h u8 *link_bw, u8 *rate_select); link_bw 137 drivers/gpu/drm/i915/display/intel_dp_link_training.c u8 link_bw, rate_select; link_bw 143 drivers/gpu/drm/i915/display/intel_dp_link_training.c &link_bw, &rate_select); link_bw 145 drivers/gpu/drm/i915/display/intel_dp_link_training.c if (link_bw) link_bw 146 drivers/gpu/drm/i915/display/intel_dp_link_training.c DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw); link_bw 151 drivers/gpu/drm/i915/display/intel_dp_link_training.c link_config[0] = link_bw; link_bw 158 drivers/gpu/drm/i915/display/intel_dp_link_training.c if (!link_bw) link_bw 49 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h int link_bw; link_bw 71 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw, link_bw 1474 drivers/gpu/drm/nouveau/nouveau_bios.c entry->dpconf.link_bw = 162000; link_bw 1477 drivers/gpu/drm/nouveau/nouveau_bios.c entry->dpconf.link_bw = 270000; link_bw 1480 drivers/gpu/drm/nouveau/nouveau_bios.c entry->dpconf.link_bw = 540000; link_bw 1484 drivers/gpu/drm/nouveau/nouveau_bios.c entry->dpconf.link_bw = 810000; link_bw 1065 drivers/gpu/drm/nouveau/nouveau_connector.c max_clock *= nv_encoder->dp.link_bw; link_bw 75 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_bw = 27000 * dpcd[1]; link_bw 79 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); link_bw 82 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dcb->dpconf.link_bw); link_bw 86 drivers/gpu/drm/nouveau/nouveau_dp.c if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) link_bw 87 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; link_bw 90 drivers/gpu/drm/nouveau/nouveau_dp.c nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); link_bw 65 drivers/gpu/drm/nouveau/nouveau_encoder.h int link_bw; link_bw 351 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c const u8 outp_bw = dp->outp.info.dpconf.link_bw; link_bw 147 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c outp->dpconf.link_bw = 0x06; link_bw 150 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c outp->dpconf.link_bw = 0x0a; link_bw 153 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c outp->dpconf.link_bw = 0x14; link_bw 157 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c outp->dpconf.link_bw = 0x1e; link_bw 193 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c int link_nr, int link_bw, bool enh) link_bw 201 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c link_nr, link_bw, enh); link_bw 203 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.c nvkm_wri2cr(adap, aux->addr, 0xa0, link_bw); link_bw 10 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h int (*lnk_ctl)(struct nvkm_i2c_aux *, int link_nr, int link_bw, link_bw 1063 include/drm/drm_dp_helper.h int drm_dp_bw_code_to_link_rate(u8 link_bw);