LVTMA_PWRSEQ_REF_DIV  350 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
LVTMA_PWRSEQ_REF_DIV  373 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
LVTMA_PWRSEQ_REF_DIV  392 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 		REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
LVTMA_PWRSEQ_REF_DIV   37 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SR(LVTMA_PWRSEQ_REF_DIV), \
LVTMA_PWRSEQ_REF_DIV   98 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
LVTMA_PWRSEQ_REF_DIV  211 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	uint32_t LVTMA_PWRSEQ_REF_DIV;