LVTMA_PWRSEQ_CNTL   31 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(LVTMA_PWRSEQ_CNTL), \
LVTMA_PWRSEQ_CNTL  337 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t LVTMA_PWRSEQ_CNTL;
LVTMA_PWRSEQ_CNTL  473 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
LVTMA_PWRSEQ_CNTL  474 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
LVTMA_PWRSEQ_CNTL  475 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
LVTMA_PWRSEQ_CNTL  682 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
LVTMA_PWRSEQ_CNTL  702 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
LVTMA_PWRSEQ_CNTL  714 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);