LVL 245 arch/arc/include/asm/entry-compact.h .macro INTERRUPT_PROLOGUE LVL LVL 297 arch/arc/include/asm/entry-compact.h .macro INTERRUPT_EPILOGUE LVL LVL 164 arch/powerpc/perf/isa207-common.c ret = PH(LVL, L1); LVL 167 arch/powerpc/perf/isa207-common.c ret = PH(LVL, L2); LVL 170 arch/powerpc/perf/isa207-common.c ret = PH(LVL, L3); LVL 174 arch/powerpc/perf/isa207-common.c ret = PH(LVL, LOC_RAM); LVL 176 arch/powerpc/perf/isa207-common.c ret = PH(LVL, REM_RAM1); LVL 178 arch/powerpc/perf/isa207-common.c ret = PH(LVL, REM_RAM2); LVL 182 arch/powerpc/perf/isa207-common.c ret = PH(LVL, REM_CCE1); LVL 189 arch/powerpc/perf/isa207-common.c ret = PH(LVL, REM_CCE2); LVL 196 arch/powerpc/perf/isa207-common.c ret = PM(LVL, L1); LVL 215 arch/powerpc/perf/isa207-common.h #define PH(a, b) (P(LVL, HIT) | P(a, b)) LVL 216 arch/powerpc/perf/isa207-common.h #define PM(a, b) (P(LVL, MISS) | P(a, b)) LVL 55 arch/x86/events/intel/ds.c #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) LVL 62 arch/x86/events/intel/ds.c P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ LVL 63 arch/x86/events/intel/ds.c OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */ LVL 64 arch/x86/events/intel/ds.c OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ LVL 65 arch/x86/events/intel/ds.c OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ LVL 66 arch/x86/events/intel/ds.c OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ LVL 67 arch/x86/events/intel/ds.c OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ LVL 68 arch/x86/events/intel/ds.c OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ LVL 69 arch/x86/events/intel/ds.c OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ LVL 70 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ LVL 71 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ LVL 72 arch/x86/events/intel/ds.c OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ LVL 73 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ LVL 74 arch/x86/events/intel/ds.c OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */ LVL 75 arch/x86/events/intel/ds.c OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */ LVL 76 arch/x86/events/intel/ds.c OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */ LVL 77 arch/x86/events/intel/ds.c OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */ LVL 83 arch/x86/events/intel/ds.c pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); LVL 84 arch/x86/events/intel/ds.c pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); LVL 85 arch/x86/events/intel/ds.c pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); LVL 102 arch/x86/events/intel/ds.c u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); LVL 124 arch/x86/events/intel/ds.c val |= P(LVL, HIT); LVL 126 arch/x86/events/intel/ds.c val |= P(LVL, MISS); LVL 1382 drivers/iommu/amd_iommu.c #define DEFINE_FREE_PT_FN(LVL, FN) \ LVL 1383 drivers/iommu/amd_iommu.c static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \ LVL 277 drivers/media/dvb-frontends/bcm3510_priv.h u8 LVL :1; LVL 979 include/linux/perf_event.h PERF_MEM_S(LVL, NA) |\ LVL 149 tools/perf/util/event.h PERF_MEM_S(LVL, NA) |\ LVL 348 tools/perf/util/mem-events.c if (lvl & P(LVL, HIT)) { LVL 349 tools/perf/util/mem-events.c if (lvl & P(LVL, UNC)) stats->ld_uncache++; LVL 350 tools/perf/util/mem-events.c if (lvl & P(LVL, IO)) stats->ld_io++; LVL 351 tools/perf/util/mem-events.c if (lvl & P(LVL, LFB)) stats->ld_fbhit++; LVL 352 tools/perf/util/mem-events.c if (lvl & P(LVL, L1 )) stats->ld_l1hit++; LVL 353 tools/perf/util/mem-events.c if (lvl & P(LVL, L2 )) stats->ld_l2hit++; LVL 354 tools/perf/util/mem-events.c if (lvl & P(LVL, L3 )) { LVL 361 tools/perf/util/mem-events.c if (lvl & P(LVL, LOC_RAM)) { LVL 369 tools/perf/util/mem-events.c if ((lvl & P(LVL, REM_RAM1)) || LVL 370 tools/perf/util/mem-events.c (lvl & P(LVL, REM_RAM2)) || LVL 380 tools/perf/util/mem-events.c if ((lvl & P(LVL, REM_CCE1)) || LVL 381 tools/perf/util/mem-events.c (lvl & P(LVL, REM_CCE2)) || LVL 389 tools/perf/util/mem-events.c if ((lvl & P(LVL, MISS))) LVL 401 tools/perf/util/mem-events.c if (lvl & P(LVL, HIT)) { LVL 402 tools/perf/util/mem-events.c if (lvl & P(LVL, UNC)) stats->st_uncache++; LVL 403 tools/perf/util/mem-events.c if (lvl & P(LVL, L1 )) stats->st_l1hit++; LVL 405 tools/perf/util/mem-events.c if (lvl & P(LVL, MISS)) LVL 406 tools/perf/util/mem-events.c if (lvl & P(LVL, L1)) stats->st_l1miss++;