levels            184 arch/arm64/include/asm/kvm_arm.h #define VTCR_EL2_LVLS_TO_SL0(levels)	\
levels            185 arch/arm64/include/asm/kvm_arm.h 	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
levels            257 arch/arm64/include/asm/kvm_arm.h #define ARM64_VTTBR_X(ipa, levels)	((ipa) - ((levels) * (PAGE_SHIFT - 3)))
levels            576 arch/arm64/include/asm/kvm_mmu.h static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels)
levels            578 arch/arm64/include/asm/kvm_mmu.h 	int x = ARM64_VTTBR_X(ipa_shift, levels);
levels            583 arch/arm64/include/asm/kvm_mmu.h static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels)
levels            585 arch/arm64/include/asm/kvm_mmu.h 	unsigned int x = arm64_vttbr_x(ipa_shift, levels);
levels            214 arch/ia64/kernel/palinfo.c 	unsigned long i, levels, unique_caches;
levels            219 arch/ia64/kernel/palinfo.c 	if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) {
levels            225 arch/ia64/kernel/palinfo.c 		   levels, unique_caches);
levels            227 arch/ia64/kernel/palinfo.c 	for (i=0; i < levels; i++) {
levels            878 arch/ia64/kernel/setup.c 	unsigned long l, levels, unique_caches;
levels            882 arch/ia64/kernel/setup.c         status = ia64_pal_cache_summary(&levels, &unique_caches);
levels            894 arch/ia64/kernel/setup.c 	for (l = 0; l < levels; ++l) {
levels            306 arch/ia64/kernel/topology.c 	unsigned long i, levels, unique_caches;
levels            313 arch/ia64/kernel/topology.c 	if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) {
levels            323 arch/ia64/kernel/topology.c 	for (i=0; i < levels; i++) {
levels            549 arch/ia64/pci/pci.c 	unsigned long levels, unique_caches;
levels            553 arch/ia64/pci/pci.c 	status = ia64_pal_cache_summary(&levels, &unique_caches);
levels            560 arch/ia64/pci/pci.c 	status = ia64_pal_cache_config_info(levels - 1,
levels             24 arch/mips/kernel/cacheinfo.c 	int levels = 0, leaves = 0;
levels             31 arch/mips/kernel/cacheinfo.c 		levels += 1;
levels             39 arch/mips/kernel/cacheinfo.c 		levels++;
levels             44 arch/mips/kernel/cacheinfo.c 		levels++;
levels             48 arch/mips/kernel/cacheinfo.c 	this_cpu_ci->num_levels = levels;
levels            166 arch/powerpc/include/asm/iommu.h 			__u32 levels);
levels            171 arch/powerpc/include/asm/iommu.h 			__u32 levels,
levels            276 arch/powerpc/platforms/powernv/npu-dma.c 		int num, __u32 page_shift, __u64 window_size, __u32 levels,
levels            289 arch/powerpc/platforms/powernv/npu-dma.c 			window_size, levels, ptbl);
levels             53 arch/powerpc/platforms/powernv/pci-ioda-tce.c 		unsigned long size, unsigned int levels);
levels            190 arch/powerpc/platforms/powernv/pci-ioda-tce.c 		unsigned long size, unsigned int levels)
levels            195 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	if (levels) {
levels            206 arch/powerpc/platforms/powernv/pci-ioda-tce.c 					levels - 1);
levels            230 arch/powerpc/platforms/powernv/pci-ioda-tce.c 		unsigned int levels, unsigned long limit,
levels            241 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	--levels;
levels            242 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	if (!levels) {
levels            249 arch/powerpc/platforms/powernv/pci-ioda-tce.c 				levels, limit, current_offset, total_allocated);
levels            264 arch/powerpc/platforms/powernv/pci-ioda-tce.c 		__u32 page_shift, __u64 window_size, __u32 levels,
levels            276 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
levels            283 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	entries_shift = (entries_shift + levels - 1) / levels;
levels            287 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	if ((level_shift - 3) * levels + page_shift >= 55)
levels            303 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	if (levels == 1 && offset < tce_table_size)
levels            314 arch/powerpc/platforms/powernv/pci-ioda-tce.c 		if (levels == 1 && (offset < tce_table_size ||
levels            323 arch/powerpc/platforms/powernv/pci-ioda-tce.c 	tbl->it_indirect_levels = levels - 1;
levels            329 arch/powerpc/platforms/powernv/pci-ioda-tce.c 			tbl->it_userspace, 1, levels);
levels            335 arch/powerpc/platforms/powernv/pci-ioda-tce.c 			1ULL << (level_shift - 3), levels - 1);
levels            338 arch/powerpc/platforms/powernv/pci-ioda-tce.c 			1ULL << (level_shift - 3), levels - 1);
levels           2363 arch/powerpc/platforms/powernv/pci-ioda.c 		int num, __u32 page_shift, __u64 window_size, __u32 levels,
levels           2381 arch/powerpc/platforms/powernv/pci-ioda.c 			levels, alloc_userspace_copy, tbl);
levels           2424 arch/powerpc/platforms/powernv/pci-ioda.c 	unsigned int levels = tces_order / tcelevel_order;
levels           2427 arch/powerpc/platforms/powernv/pci-ioda.c 		levels += 1;
levels           2432 arch/powerpc/platforms/powernv/pci-ioda.c 	levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
levels           2435 arch/powerpc/platforms/powernv/pci-ioda.c 			window_size, levels, false, &tbl);
levels           2501 arch/powerpc/platforms/powernv/pci-ioda.c 		__u64 window_size, __u32 levels)
levels           2510 arch/powerpc/platforms/powernv/pci-ioda.c 	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
levels           2515 arch/powerpc/platforms/powernv/pci-ioda.c 	entries_shift = (entries_shift + levels - 1) / levels;
levels           2520 arch/powerpc/platforms/powernv/pci-ioda.c 	for ( ; levels; --levels) {
levels           2534 arch/powerpc/platforms/powernv/pci-ioda.c 		int num, __u32 page_shift, __u64 window_size, __u32 levels,
levels           2538 arch/powerpc/platforms/powernv/pci-ioda.c 			num, page_shift, window_size, levels, true, ptbl);
levels           2542 arch/powerpc/platforms/powernv/pci-ioda.c 				page_shift, window_size, levels);
levels            199 arch/powerpc/platforms/powernv/pci.h 		__u64 window_size, __u32 levels);
levels            237 arch/powerpc/platforms/powernv/pci.h 		__u32 page_shift, __u64 window_size, __u32 levels,
levels             24 arch/riscv/kernel/cacheinfo.c 	int levels = 0, leaves = 0, level;
levels             33 arch/riscv/kernel/cacheinfo.c 		levels = 1;
levels             43 arch/riscv/kernel/cacheinfo.c 		if (level <= levels)
levels             51 arch/riscv/kernel/cacheinfo.c 		levels = level;
levels             55 arch/riscv/kernel/cacheinfo.c 	this_cpu_ci->num_levels = levels;
levels             67 arch/riscv/kernel/cacheinfo.c 	int levels = 1, level = 1;
levels             84 arch/riscv/kernel/cacheinfo.c 		if (level <= levels)
levels             92 arch/riscv/kernel/cacheinfo.c 		levels = level;
levels            229 arch/sparc/kernel/sun4d_smp.c #define IGEN_MESSAGE(bcast, devid, sid, levels) \
levels            230 arch/sparc/kernel/sun4d_smp.c 	(((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
levels            219 arch/x86/kernel/cpu/cacheinfo.c static const unsigned char levels[] = { 1, 1, 2, 3 };
levels            287 arch/x86/kernel/cpu/cacheinfo.c 	eax->split.level = levels[leaf];
levels             98 arch/x86/kernel/cpu/microcode/core.c 	u32 *levels;
levels            103 arch/x86/kernel/cpu/microcode/core.c 		levels = (u32 *)__pa_nodebug(&final_levels);
levels            105 arch/x86/kernel/cpu/microcode/core.c 		levels = final_levels;
levels            107 arch/x86/kernel/cpu/microcode/core.c 	for (i = 0; levels[i]; i++) {
levels            108 arch/x86/kernel/cpu/microcode/core.c 		if (lvl == levels[i])
levels           2005 block/blk-iocost.c 	int levels = blkcg->css.cgroup->level + 1;
levels           2008 block/blk-iocost.c 	iocg = kzalloc_node(sizeof(*iocg) + levels * sizeof(iocg->ancestors[0]),
levels            238 drivers/acpi/acpi_video.c 		if (vd->brightness->levels[i] == cur_level)
levels            251 drivers/acpi/acpi_video.c 				vd->brightness->levels[request_level]);
levels            282 drivers/acpi/acpi_video.c 		if (level == video->brightness->levels[offset]) {
levels            301 drivers/acpi/acpi_video.c 	level = video->brightness->levels[state - 1];
levels            319 drivers/acpi/acpi_video.c 				   union acpi_object **levels)
levels            326 drivers/acpi/acpi_video.c 	*levels = NULL;
levels            338 drivers/acpi/acpi_video.c 	*levels = obj;
levels            364 drivers/acpi/acpi_video.c 		if (level == device->brightness->levels[state]) {
levels            580 drivers/acpi/acpi_video.c 		level = device->brightness->levels[bqc_value +
levels            617 drivers/acpi/acpi_video.c 				if (device->brightness->levels[i] == *level) {
levels            788 drivers/acpi/acpi_video.c 		? br->levels[ACPI_VIDEO_FIRST_LEVEL + 1]
levels            804 drivers/acpi/acpi_video.c 			if (br->levels[level + ACPI_VIDEO_FIRST_LEVEL] == test_level)
levels            851 drivers/acpi/acpi_video.c 	br->levels = kmalloc_array(obj->package.count + ACPI_VIDEO_FIRST_LEVEL,
levels            852 drivers/acpi/acpi_video.c 				   sizeof(*br->levels),
levels            854 drivers/acpi/acpi_video.c 	if (!br->levels) {
levels            868 drivers/acpi/acpi_video.c 		    && br->levels[count - 1] == value)
levels            871 drivers/acpi/acpi_video.c 		br->levels[count] = value;
levels            873 drivers/acpi/acpi_video.c 		if (br->levels[count] > max_level)
levels            874 drivers/acpi/acpi_video.c 			max_level = br->levels[count];
levels            885 drivers/acpi/acpi_video.c 		if (br->levels[i] == br->levels[ACPI_VIDEO_AC_LEVEL])
levels            887 drivers/acpi/acpi_video.c 		if (br->levels[i] == br->levels[ACPI_VIDEO_BATTERY_LEVEL])
levels            896 drivers/acpi/acpi_video.c 			br->levels[i] = br->levels[i - level_ac_battery];
levels            902 drivers/acpi/acpi_video.c 	if (max_level == br->levels[ACPI_VIDEO_FIRST_LEVEL]) {
levels            904 drivers/acpi/acpi_video.c 		sort(&br->levels[ACPI_VIDEO_FIRST_LEVEL],
levels            906 drivers/acpi/acpi_video.c 		     sizeof(br->levels[ACPI_VIDEO_FIRST_LEVEL]),
levels            908 drivers/acpi/acpi_video.c 	} else if (max_level != br->levels[count - 1])
levels            978 drivers/acpi/acpi_video.c 		if (level == br->levels[i])
levels            994 drivers/acpi/acpi_video.c 	kfree(br->levels);
levels           1382 drivers/acpi/acpi_video.c 		l = device->brightness->levels[i];
levels           1392 drivers/acpi/acpi_video.c 		l = device->brightness->levels[i];
levels           1821 drivers/acpi/acpi_video.c 	union acpi_object *levels;
levels           1825 drivers/acpi/acpi_video.c 		if (!acpi_video_device_lcd_query_levels(dev->dev->handle, &levels))
levels           1826 drivers/acpi/acpi_video.c 			kfree(levels);
levels           1880 drivers/acpi/acpi_video.c 		kfree(device->brightness->levels);
levels           1782 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
levels           1790 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
levels           1796 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
levels           1797 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
levels           1807 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
levels           1816 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			    new_ps->levels[new_ps->num_levels - 1].sclk)
levels           1822 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			if ((new_ps->levels[0].sclk -
levels           1825 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			     new_ps->levels[new_ps->num_levels -1].sclk))
levels           2255 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		if (ps->levels[i].sclk < sclk)
levels           2256 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			ps->levels[i].sclk = sclk;
levels           2263 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			     kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
levels           2265 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 				ps->levels[i].sclk = table->entries[limit].clk;
levels           2275 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			     kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
levels           2277 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 				ps->levels[i].sclk = table->entries[limit].sclk_frequency;
levels           2284 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			ps->levels[i].sclk = stable_p_state_sclk;
levels           2649 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	ps->levels[0] = pi->boot_pl;
levels           2685 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 	struct kv_pl *pl = &ps->levels[index];
levels           2903 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		struct kv_pl *pl = &ps->levels[i];
levels           2935 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		return requested_state->levels[0].sclk;
levels           2937 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		return requested_state->levels[requested_state->num_levels - 1].sclk;
levels           3266 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 		if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
levels           3267 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 					&(kv_rps->levels[i]))) {
levels            108 drivers/gpu/drm/amd/amdgpu/kv_dpm.h 	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
levels           2415 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[0].dpm2.MaxPS = 0;
levels           2416 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[0].dpm2.NearTDPDec = 0;
levels           2417 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[0].dpm2.AboveSafeInc = 0;
levels           2418 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[0].dpm2.BelowSafeInc = 0;
levels           2419 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
levels           2468 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
levels           2469 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
levels           2470 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
levels           2471 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
levels           2472 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
levels           2528 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
levels           2529 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
levels           3866 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 levels = ps->performance_level_count;
levels           3869 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
levels           3884 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
levels           4841 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vDLL_CNTL =
levels           4843 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
levels           4845 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
levels           4847 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
levels           4849 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
levels           4851 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
levels           4853 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
levels           4855 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_SS =
levels           4857 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_SS2 =
levels           4860 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].mclk.mclk_value =
levels           4863 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           4865 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           4867 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           4869 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
levels           4871 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
levels           4873 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
levels           4876 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].sclk.sclk_value =
levels           4879 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].arbRefreshState =
levels           4882 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].ACIndex = 0;
levels           4886 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					&table->initialState.levels[0].vddc);
levels           4892 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					       &table->initialState.levels[0].vddc,
levels           4896 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						      table->initialState.levels[0].vddc.index,
levels           4897 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						      &table->initialState.levels[0].std_vddc);
levels           4904 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					  &table->initialState.levels[0].vddci);
levels           4912 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						 &table->initialState.levels[0].vddc);
levels           4914 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
levels           4917 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].aT = cpu_to_be32(reg);
levels           4918 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
levels           4919 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
levels           4922 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		table->initialState.levels[0].strobeMode =
levels           4927 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
levels           4929 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			table->initialState.levels[0].mcFlags =  0;
levels           4936 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].dpm2.MaxPS = 0;
levels           4937 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].dpm2.NearTDPDec = 0;
levels           4938 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].dpm2.AboveSafeInc = 0;
levels           4939 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].dpm2.BelowSafeInc = 0;
levels           4940 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
levels           4943 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
levels           4946 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
levels           4977 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
levels           4982 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						       &table->ACPIState.levels[0].vddc, &std_vddc);
levels           4985 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							      table->ACPIState.levels[0].vddc.index,
levels           4986 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							      &table->ACPIState.levels[0].std_vddc);
levels           4988 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
levels           4996 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							 &table->ACPIState.levels[0].vddc);
levels           5000 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
levels           5005 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						       &table->ACPIState.levels[0].vddc, &std_vddc);
levels           5009 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							      table->ACPIState.levels[0].vddc.index,
levels           5010 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							      &table->ACPIState.levels[0].std_vddc);
levels           5012 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		table->ACPIState.levels[0].gen2PCIE =
levels           5024 drivers/gpu/drm/amd/amdgpu/si_dpm.c 							 &table->ACPIState.levels[0].vddc);
levels           5031 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						  &table->ACPIState.levels[0].vddci);
levels           5042 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vDLL_CNTL =
levels           5044 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
levels           5046 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
levels           5048 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
levels           5050 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
levels           5052 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
levels           5054 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
levels           5056 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_SS =
levels           5058 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_SS2 =
levels           5061 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           5063 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           5065 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           5067 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
levels           5070 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].mclk.mclk_value = 0;
levels           5071 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels           5073 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
levels           5076 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		table->ACPIState.levels[0].ACIndex = 0;
levels           5078 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].dpm2.MaxPS = 0;
levels           5079 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
levels           5080 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
levels           5081 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
levels           5082 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
levels           5085 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
levels           5088 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
levels           5103 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					    &state->levels[0]);
levels           5107 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
levels           5109 drivers/gpu/drm/amd/amdgpu/si_dpm.c 				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
levels           5113 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
levels           5114 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		state->levels[0].ACIndex = 1;
levels           5115 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		state->levels[0].std_vddc = state->levels[0].vddc;
levels           5433 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
levels           5435 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[ps->performance_level_count - 1].bSP =
levels           5564 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[0].aT = cpu_to_be32(a_t);
levels           5568 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	smc_state->levels[0].aT = cpu_to_be32(0);
levels           5584 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
levels           5586 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].aT = cpu_to_be32(a_t);
levels           5591 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
levels           5684 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
levels           5686 drivers/gpu/drm/amd/amdgpu/si_dpm.c 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
levels           5691 drivers/gpu/drm/amd/amdgpu/si_dpm.c 						    &smc_state->levels[i]);
levels           5692 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		smc_state->levels[i].arbRefreshState =
levels           5699 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			smc_state->levels[i].displayWatermark =
levels           5703 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			smc_state->levels[i].displayWatermark = (i < 2) ?
levels           5707 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
levels           5709 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			smc_state->levels[i].ACIndex = 0;
levels            458 drivers/gpu/drm/amd/amdgpu/si_dpm.h     RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
levels            784 drivers/gpu/drm/amd/amdgpu/si_dpm.h     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
levels            189 drivers/gpu/drm/amd/amdgpu/sislands_smc.h     SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
levels            755 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->levels[index].engine_clock = 0;
levels            757 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_ps->levels[index].vddc_index = 0;
levels            761 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_ps->levels[index].ds_divider_index = 5;
levels            762 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_ps->levels[index].ss_divider_index = 5;
levels            961 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
levels            962 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
levels            146 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h 	struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS];
levels           1314 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		return smu8_ps->levels[0].engineClock;
levels           1316 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		return smu8_ps->levels[smu8_ps->level-1].engineClock;
levels           1328 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_ps->levels[0] = data->boot_power_level;
levels           1350 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
levels           1351 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
levels           1356 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_ps->levels[index].dsDividerIndex = 5;
levels           1357 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_ps->levels[index].ssDividerIndex = 5;
levels           1567 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level->coreClock = ps->levels[level_index].engineClock;
levels           1571 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
levels           1572 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				level->coreClock = ps->levels[i].engineClock;
levels           1583 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
levels           1595 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
levels           1596 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
levels            159 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.h 	struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS];
levels            480 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct SMU7_Discrete_GraphicsLevel *levels =
levels            487 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				&levels[i]);
levels            504 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				   (u8 *)levels, array_size,
levels           1309 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
levels           1312 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	memset(levels, 0x00, level_array_size);
levels           1342 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
levels           2764 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct SMU7_Discrete_GraphicsLevel *levels =
levels           2785 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (levels[i].ActivityLevel !=
levels           2787 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
levels           2793 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
levels           2797 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (levels[i].UpH != setting->sclk_up_hyst ||
levels           2798 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				levels[i].DownH != setting->sclk_down_hyst) {
levels           2799 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				levels[i].UpH = setting->sclk_up_hyst;
levels           2800 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				levels[i].DownH = setting->sclk_down_hyst;
levels           2807 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));
levels           2808 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));
levels           1018 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct SMU73_Discrete_GraphicsLevel *levels =
levels           1029 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				&levels[i]);
levels           1035 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			levels[i].DeepSleepDivId = 0;
levels           1039 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	levels[0].EnabledForActivity = 1;
levels           1042 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
levels           1056 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			levels[i].pcieDpmLevel =
levels           1081 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
levels           1084 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
levels           1087 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
levels           1090 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
levels           1234 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct SMU73_Discrete_MemoryLevel *levels =
levels           1244 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				&levels[i]);
levels           1250 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	levels[0].EnabledForActivity = 1;
levels           1257 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
levels           1258 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
levels           1265 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
levels           1269 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
levels           2556 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct SMU73_Discrete_GraphicsLevel *levels =
levels           2577 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			if (levels[i].ActivityLevel !=
levels           2579 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
levels           2585 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
levels           2589 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			if (levels[i].UpHyst != setting->sclk_up_hyst ||
levels           2590 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				levels[i].DownHyst != setting->sclk_down_hyst) {
levels           2591 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				levels[i].UpHyst = setting->sclk_up_hyst;
levels           2592 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				levels[i].DownHyst = setting->sclk_down_hyst;
levels           2599 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
levels           2600 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
levels            970 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
levels            978 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	memset(levels, 0x00, level_array_size);
levels           1038 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				(uint8_t *)levels, (uint32_t)level_array_size,
levels           1356 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
levels           1359 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	memset(levels, 0x00, level_array_size);
levels           1389 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
levels            991 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct SMU74_Discrete_GraphicsLevel *levels =
levels           1011 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			levels[i].DeepSleepDivId = 0;
levels           1030 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			levels[i].pcieDpmLevel =
levels           1055 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
levels           1058 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
levels           1061 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
levels           1064 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
levels           1135 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct SMU74_Discrete_MemoryLevel *levels =
levels           1145 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				&levels[i]);
levels           1147 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
levels           1148 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			levels[i].EnabledForActivity = 1;
levels           1159 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	levels[0].ActivityLevel = 0x1f;
levels           1160 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
levels           1168 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
levels           2469 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct SMU74_Discrete_GraphicsLevel *levels =
levels           2490 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			if (levels[i].ActivityLevel !=
levels           2492 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
levels           2498 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
levels           2502 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			if (levels[i].UpHyst != setting->sclk_up_hyst ||
levels           2503 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				levels[i].DownHyst != setting->sclk_down_hyst) {
levels           2504 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				levels[i].UpHyst = setting->sclk_up_hyst;
levels           2505 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				levels[i].DownHyst = setting->sclk_down_hyst;
levels           2512 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
levels           2513 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
levels            700 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
levels            708 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	memset(levels, 0x00, level_array_size);
levels            781 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(uint8_t *)levels, (uint32_t)level_array_size,
levels           1101 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	SMU72_Discrete_MemoryLevel *levels =
levels           1105 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	memset(levels, 0x00, level_array_size);
levels           1137 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
levels           3152 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct SMU72_Discrete_GraphicsLevel *levels =
levels           3173 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			if (levels[i].ActivityLevel !=
levels           3175 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
levels           3181 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
levels           3185 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			if (levels[i].UpHyst != setting->sclk_up_hyst ||
levels           3186 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				levels[i].DownHyst != setting->sclk_down_hyst) {
levels           3187 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				levels[i].UpHyst = setting->sclk_up_hyst;
levels           3188 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				levels[i].DownHyst = setting->sclk_down_hyst;
levels           3195 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
levels           3196 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
levels            875 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct SMU75_Discrete_GraphicsLevel *levels =
levels            893 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[i].UpHyst = (uint8_t)
levels            895 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[i].DownHyst = (uint8_t)
levels            899 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			levels[i].DeepSleepDivId = 0;
levels            911 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[i].EnabledForActivity =
levels            920 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			levels[i].pcieDpmLevel =
levels            945 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
levels            948 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
levels            951 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
levels            954 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
levels           1042 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct SMU75_Discrete_MemoryLevel *levels =
levels           1052 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				&levels[i]);
levels           1057 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[i].UpHyst = (uint8_t)
levels           1059 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[i].DownHyst = (uint8_t)
levels           1069 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		levels[i].EnabledForActivity =
levels           1072 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
levels           1076 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
levels           2077 drivers/gpu/drm/i915/gvt/gtt.c 	int i, levels = 0;
levels           2103 drivers/gpu/drm/i915/gvt/gtt.c 			levels = 4;
levels           2111 drivers/gpu/drm/i915/gvt/gtt.c 			levels = 2;
levels           2118 drivers/gpu/drm/i915/gvt/gtt.c 		for (i = 0; i < levels; i++) {
levels           2120 drivers/gpu/drm/i915/gvt/gtt.c 				(i == levels - 1));
levels           4893 drivers/gpu/drm/i915/intel_pm.c 		      struct skl_wm_level *levels)
levels           4897 drivers/gpu/drm/i915/intel_pm.c 	struct skl_wm_level *result_prev = &levels[0];
levels           4900 drivers/gpu/drm/i915/intel_pm.c 		struct skl_wm_level *result = &levels[level];
levels           1043 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	int levels, bits = 0, ret;
levels           1063 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	for (levels = 0, desc = page->desc; desc->bits; desc++, levels++)
levels           1068 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	if (WARN_ON(levels > NVKM_VMM_LEVELS_MAX))
levels           1408 drivers/gpu/drm/radeon/btc_dpm.c 							 &table->ULVState.levels[0],
levels           1411 drivers/gpu/drm/radeon/btc_dpm.c 			table->ULVState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
levels           1412 drivers/gpu/drm/radeon/btc_dpm.c 			table->ULVState.levels[0].ACIndex = 1;
levels           1414 drivers/gpu/drm/radeon/btc_dpm.c 			table->ULVState.levels[1] = table->ULVState.levels[0];
levels           1415 drivers/gpu/drm/radeon/btc_dpm.c 			table->ULVState.levels[2] = table->ULVState.levels[0];
levels           1433 drivers/gpu/drm/radeon/btc_dpm.c 		table->ACPIState.levels[0].ACIndex = 0;
levels           1434 drivers/gpu/drm/radeon/btc_dpm.c 		table->ACPIState.levels[1].ACIndex = 0;
levels           1435 drivers/gpu/drm/radeon/btc_dpm.c 		table->ACPIState.levels[2].ACIndex = 0;
levels           3284 drivers/gpu/drm/radeon/ci_dpm.c 	SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
levels           3287 drivers/gpu/drm/radeon/ci_dpm.c 	memset(levels, 0, level_array_size);
levels           3309 drivers/gpu/drm/radeon/ci_dpm.c 				   (u8 *)levels, level_array_size,
levels           3331 drivers/gpu/drm/radeon/ci_dpm.c 	SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
levels           3334 drivers/gpu/drm/radeon/ci_dpm.c 	memset(levels, 0, level_array_size);
levels           3366 drivers/gpu/drm/radeon/ci_dpm.c 				   (u8 *)levels, level_array_size,
levels           4210 drivers/gpu/drm/radeon/ci_dpm.c 	u32 tmp, levels, i;
levels           4216 drivers/gpu/drm/radeon/ci_dpm.c 			levels = 0;
levels           4219 drivers/gpu/drm/radeon/ci_dpm.c 				levels++;
levels           4220 drivers/gpu/drm/radeon/ci_dpm.c 			if (levels) {
levels           4227 drivers/gpu/drm/radeon/ci_dpm.c 					if (tmp == levels)
levels           4235 drivers/gpu/drm/radeon/ci_dpm.c 			levels = 0;
levels           4238 drivers/gpu/drm/radeon/ci_dpm.c 				levels++;
levels           4239 drivers/gpu/drm/radeon/ci_dpm.c 			if (levels) {
levels           4240 drivers/gpu/drm/radeon/ci_dpm.c 				ret = ci_dpm_force_state_sclk(rdev, levels);
levels           4246 drivers/gpu/drm/radeon/ci_dpm.c 					if (tmp == levels)
levels           4254 drivers/gpu/drm/radeon/ci_dpm.c 			levels = 0;
levels           4257 drivers/gpu/drm/radeon/ci_dpm.c 				levels++;
levels           4258 drivers/gpu/drm/radeon/ci_dpm.c 			if (levels) {
levels           4259 drivers/gpu/drm/radeon/ci_dpm.c 				ret = ci_dpm_force_state_mclk(rdev, levels);
levels           4265 drivers/gpu/drm/radeon/ci_dpm.c 					if (tmp == levels)
levels           4274 drivers/gpu/drm/radeon/ci_dpm.c 			levels = ci_get_lowest_enabled_level(rdev,
levels           4276 drivers/gpu/drm/radeon/ci_dpm.c 			ret = ci_dpm_force_state_sclk(rdev, levels);
levels           4282 drivers/gpu/drm/radeon/ci_dpm.c 				if (tmp == levels)
levels           4289 drivers/gpu/drm/radeon/ci_dpm.c 			levels = ci_get_lowest_enabled_level(rdev,
levels           4291 drivers/gpu/drm/radeon/ci_dpm.c 			ret = ci_dpm_force_state_mclk(rdev, levels);
levels           4297 drivers/gpu/drm/radeon/ci_dpm.c 				if (tmp == levels)
levels           4304 drivers/gpu/drm/radeon/ci_dpm.c 			levels = ci_get_lowest_enabled_level(rdev,
levels           4306 drivers/gpu/drm/radeon/ci_dpm.c 			ret = ci_dpm_force_state_pcie(rdev, levels);
levels           4312 drivers/gpu/drm/radeon/ci_dpm.c 				if (tmp == levels)
levels            776 drivers/gpu/drm/radeon/cypress_dpm.c 						 &smc_state->levels[0],
levels            783 drivers/gpu/drm/radeon/cypress_dpm.c 						 &smc_state->levels[1],
levels            790 drivers/gpu/drm/radeon/cypress_dpm.c 						 &smc_state->levels[2],
levels            795 drivers/gpu/drm/radeon/cypress_dpm.c 	smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
levels            796 drivers/gpu/drm/radeon/cypress_dpm.c 	smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
levels            797 drivers/gpu/drm/radeon/cypress_dpm.c 	smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
levels            800 drivers/gpu/drm/radeon/cypress_dpm.c 		smc_state->levels[0].ACIndex = 2;
levels            801 drivers/gpu/drm/radeon/cypress_dpm.c 		smc_state->levels[1].ACIndex = 3;
levels            802 drivers/gpu/drm/radeon/cypress_dpm.c 		smc_state->levels[2].ACIndex = 4;
levels            804 drivers/gpu/drm/radeon/cypress_dpm.c 		smc_state->levels[0].ACIndex = 0;
levels            805 drivers/gpu/drm/radeon/cypress_dpm.c 		smc_state->levels[1].ACIndex = 0;
levels            806 drivers/gpu/drm/radeon/cypress_dpm.c 		smc_state->levels[2].ACIndex = 0;
levels           1244 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
levels           1246 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
levels           1248 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
levels           1250 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
levels           1252 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
levels           1254 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
levels           1257 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
levels           1259 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
levels           1262 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].mclk.mclk770.mclk_value =
levels           1265 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           1267 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           1269 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           1271 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
levels           1273 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
levels           1276 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].sclk.sclk_value =
levels           1279 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
levels           1281 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].ACIndex = 0;
levels           1286 drivers/gpu/drm/radeon/cypress_dpm.c 				       &table->initialState.levels[0].vddc);
levels           1292 drivers/gpu/drm/radeon/cypress_dpm.c 					       &table->initialState.levels[0].vddci);
levels           1295 drivers/gpu/drm/radeon/cypress_dpm.c 					    &table->initialState.levels[0].mvdd);
levels           1298 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].aT = cpu_to_be32(a_t);
levels           1300 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
levels           1304 drivers/gpu/drm/radeon/cypress_dpm.c 		table->initialState.levels[0].gen2PCIE = 1;
levels           1306 drivers/gpu/drm/radeon/cypress_dpm.c 		table->initialState.levels[0].gen2PCIE = 0;
levels           1308 drivers/gpu/drm/radeon/cypress_dpm.c 		table->initialState.levels[0].gen2XSP = 1;
levels           1310 drivers/gpu/drm/radeon/cypress_dpm.c 		table->initialState.levels[0].gen2XSP = 0;
levels           1313 drivers/gpu/drm/radeon/cypress_dpm.c 		table->initialState.levels[0].strobeMode =
levels           1318 drivers/gpu/drm/radeon/cypress_dpm.c 			table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
levels           1320 drivers/gpu/drm/radeon/cypress_dpm.c 			table->initialState.levels[0].mcFlags =  0;
levels           1323 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[1] = table->initialState.levels[0];
levels           1324 drivers/gpu/drm/radeon/cypress_dpm.c 	table->initialState.levels[2] = table->initialState.levels[0];
levels           1363 drivers/gpu/drm/radeon/cypress_dpm.c 					       &table->ACPIState.levels[0].vddc);
levels           1366 drivers/gpu/drm/radeon/cypress_dpm.c 				table->ACPIState.levels[0].gen2PCIE = 1;
levels           1368 drivers/gpu/drm/radeon/cypress_dpm.c 				table->ACPIState.levels[0].gen2PCIE = 0;
levels           1370 drivers/gpu/drm/radeon/cypress_dpm.c 			table->ACPIState.levels[0].gen2PCIE = 0;
levels           1372 drivers/gpu/drm/radeon/cypress_dpm.c 			table->ACPIState.levels[0].gen2XSP = 1;
levels           1374 drivers/gpu/drm/radeon/cypress_dpm.c 			table->ACPIState.levels[0].gen2XSP = 0;
levels           1379 drivers/gpu/drm/radeon/cypress_dpm.c 					       &table->ACPIState.levels[0].vddc);
levels           1380 drivers/gpu/drm/radeon/cypress_dpm.c 		table->ACPIState.levels[0].gen2PCIE = 0;
levels           1388 drivers/gpu/drm/radeon/cypress_dpm.c 						       &table->ACPIState.levels[0].vddci);
levels           1434 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
levels           1436 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
levels           1438 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
levels           1440 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
levels           1442 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
levels           1444 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
levels           1446 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
levels           1448 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           1450 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           1452 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           1455 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels           1457 drivers/gpu/drm/radeon/cypress_dpm.c 	cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
levels           1460 drivers/gpu/drm/radeon/cypress_dpm.c 		table->ACPIState.levels[0].ACIndex = 1;
levels           1462 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[1] = table->ACPIState.levels[0];
levels           1463 drivers/gpu/drm/radeon/cypress_dpm.c 	table->ACPIState.levels[2] = table->ACPIState.levels[0];
levels           1718 drivers/gpu/drm/radeon/kv_dpm.c 			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
levels           1726 drivers/gpu/drm/radeon/kv_dpm.c 			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
levels           1732 drivers/gpu/drm/radeon/kv_dpm.c 			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
levels           1733 drivers/gpu/drm/radeon/kv_dpm.c 			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
levels           1743 drivers/gpu/drm/radeon/kv_dpm.c 			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
levels           1752 drivers/gpu/drm/radeon/kv_dpm.c 			    new_ps->levels[new_ps->num_levels - 1].sclk)
levels           1758 drivers/gpu/drm/radeon/kv_dpm.c 			if ((new_ps->levels[0].sclk -
levels           1761 drivers/gpu/drm/radeon/kv_dpm.c 			     new_ps->levels[new_ps->num_levels -1].sclk))
levels           2190 drivers/gpu/drm/radeon/kv_dpm.c 		if (ps->levels[i].sclk < sclk)
levels           2191 drivers/gpu/drm/radeon/kv_dpm.c 			ps->levels[i].sclk = sclk;
levels           2198 drivers/gpu/drm/radeon/kv_dpm.c 			     kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
levels           2200 drivers/gpu/drm/radeon/kv_dpm.c 				ps->levels[i].sclk = table->entries[limit].clk;
levels           2210 drivers/gpu/drm/radeon/kv_dpm.c 			     kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
levels           2212 drivers/gpu/drm/radeon/kv_dpm.c 				ps->levels[i].sclk = table->entries[limit].sclk_frequency;
levels           2219 drivers/gpu/drm/radeon/kv_dpm.c 			ps->levels[i].sclk = stable_p_state_sclk;
levels           2581 drivers/gpu/drm/radeon/kv_dpm.c 	ps->levels[0] = pi->boot_pl;
levels           2617 drivers/gpu/drm/radeon/kv_dpm.c 	struct kv_pl *pl = &ps->levels[index];
levels           2859 drivers/gpu/drm/radeon/kv_dpm.c 		struct kv_pl *pl = &ps->levels[i];
levels           2890 drivers/gpu/drm/radeon/kv_dpm.c 		return requested_state->levels[0].sclk;
levels           2892 drivers/gpu/drm/radeon/kv_dpm.c 		return requested_state->levels[requested_state->num_levels - 1].sclk;
levels             82 drivers/gpu/drm/radeon/kv_dpm.h 	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
levels           1692 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
levels           1694 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
levels           1696 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
levels           1698 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
levels           1700 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
levels           1702 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vDLL_CNTL =
levels           1704 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMPLL_SS =
levels           1706 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.vMPLL_SS2 =
levels           1708 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].mclk.mclk_value =
levels           1711 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           1713 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           1715 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           1717 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
levels           1719 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
levels           1721 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
levels           1723 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].sclk.sclk_value =
levels           1725 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].arbRefreshState =
levels           1728 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].ACIndex = 0;
levels           1732 drivers/gpu/drm/radeon/ni_dpm.c 					&table->initialState.levels[0].vddc);
levels           1737 drivers/gpu/drm/radeon/ni_dpm.c 					       &table->initialState.levels[0].vddc,
levels           1741 drivers/gpu/drm/radeon/ni_dpm.c 						      table->initialState.levels[0].vddc.index,
levels           1742 drivers/gpu/drm/radeon/ni_dpm.c 						      &table->initialState.levels[0].std_vddc);
levels           1749 drivers/gpu/drm/radeon/ni_dpm.c 					  &table->initialState.levels[0].vddci);
levels           1751 drivers/gpu/drm/radeon/ni_dpm.c 	ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
levels           1754 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].aT = cpu_to_be32(reg);
levels           1756 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
levels           1759 drivers/gpu/drm/radeon/ni_dpm.c 		table->initialState.levels[0].gen2PCIE = 1;
levels           1761 drivers/gpu/drm/radeon/ni_dpm.c 		table->initialState.levels[0].gen2PCIE = 0;
levels           1764 drivers/gpu/drm/radeon/ni_dpm.c 		table->initialState.levels[0].strobeMode =
levels           1769 drivers/gpu/drm/radeon/ni_dpm.c 			table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
levels           1771 drivers/gpu/drm/radeon/ni_dpm.c 			table->initialState.levels[0].mcFlags =  0;
levels           1778 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].dpm2.MaxPS = 0;
levels           1779 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].dpm2.NearTDPDec = 0;
levels           1780 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].dpm2.AboveSafeInc = 0;
levels           1781 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].dpm2.BelowSafeInc = 0;
levels           1784 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
levels           1787 drivers/gpu/drm/radeon/ni_dpm.c 	table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
levels           1818 drivers/gpu/drm/radeon/ni_dpm.c 						pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
levels           1823 drivers/gpu/drm/radeon/ni_dpm.c 						       &table->ACPIState.levels[0].vddc, &std_vddc);
levels           1826 drivers/gpu/drm/radeon/ni_dpm.c 							      table->ACPIState.levels[0].vddc.index,
levels           1827 drivers/gpu/drm/radeon/ni_dpm.c 							      &table->ACPIState.levels[0].std_vddc);
levels           1832 drivers/gpu/drm/radeon/ni_dpm.c 				table->ACPIState.levels[0].gen2PCIE = 1;
levels           1834 drivers/gpu/drm/radeon/ni_dpm.c 				table->ACPIState.levels[0].gen2PCIE = 0;
levels           1836 drivers/gpu/drm/radeon/ni_dpm.c 			table->ACPIState.levels[0].gen2PCIE = 0;
levels           1842 drivers/gpu/drm/radeon/ni_dpm.c 						&table->ACPIState.levels[0].vddc);
levels           1847 drivers/gpu/drm/radeon/ni_dpm.c 						       &table->ACPIState.levels[0].vddc,
levels           1851 drivers/gpu/drm/radeon/ni_dpm.c 							      table->ACPIState.levels[0].vddc.index,
levels           1852 drivers/gpu/drm/radeon/ni_dpm.c 							      &table->ACPIState.levels[0].std_vddc);
levels           1854 drivers/gpu/drm/radeon/ni_dpm.c 		table->ACPIState.levels[0].gen2PCIE = 0;
levels           1862 drivers/gpu/drm/radeon/ni_dpm.c 						  &table->ACPIState.levels[0].vddci);
levels           1905 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
levels           1906 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
levels           1907 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
levels           1908 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
levels           1909 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
levels           1910 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
levels           1912 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].mclk.mclk_value = 0;
levels           1914 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
levels           1915 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
levels           1916 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
levels           1917 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
levels           1919 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels           1921 drivers/gpu/drm/radeon/ni_dpm.c 	ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
levels           1924 drivers/gpu/drm/radeon/ni_dpm.c 		table->ACPIState.levels[0].ACIndex = 1;
levels           1926 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].dpm2.MaxPS = 0;
levels           1927 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
levels           1928 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
levels           1929 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
levels           1932 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
levels           1935 drivers/gpu/drm/radeon/ni_dpm.c 	table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
levels           2303 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
levels           2305 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[ps->performance_level_count - 1].bSP =
levels           2407 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[0].aT = cpu_to_be32(a_t);
levels           2411 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[0].aT = cpu_to_be32(0);
levels           2436 drivers/gpu/drm/radeon/ni_dpm.c 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
levels           2438 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].aT = cpu_to_be32(a_t);
levels           2444 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
levels           2495 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[0].dpm2.MaxPS = 0;
levels           2496 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[0].dpm2.NearTDPDec = 0;
levels           2497 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[0].dpm2.AboveSafeInc = 0;
levels           2498 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[0].dpm2.BelowSafeInc = 0;
levels           2499 drivers/gpu/drm/radeon/ni_dpm.c 	smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;
levels           2523 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].dpm2.MaxPS =
levels           2525 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;
levels           2526 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;
levels           2527 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;
levels           2528 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].stateFlags |=
levels           2587 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].SQPowerThrottle   = cpu_to_be32(sq_power_throttle);
levels           2588 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
levels           2644 drivers/gpu/drm/radeon/ni_dpm.c 						    &smc_state->levels[i]);
levels           2645 drivers/gpu/drm/radeon/ni_dpm.c 		smc_state->levels[i].arbRefreshState =
levels           2652 drivers/gpu/drm/radeon/ni_dpm.c 			smc_state->levels[i].displayWatermark =
levels           2656 drivers/gpu/drm/radeon/ni_dpm.c 			smc_state->levels[i].displayWatermark = (i < 2) ?
levels           2660 drivers/gpu/drm/radeon/ni_dpm.c 			smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
levels           2662 drivers/gpu/drm/radeon/ni_dpm.c 			smc_state->levels[i].ACIndex = 0;
levels            141 drivers/gpu/drm/radeon/nislands_smc.h     NISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
levels            246 drivers/gpu/drm/radeon/rv730_dpm.c 					  &table->ACPIState.levels[0].vddc);
levels            247 drivers/gpu/drm/radeon/rv730_dpm.c 		table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
levels            249 drivers/gpu/drm/radeon/rv730_dpm.c 		table->ACPIState.levels[0].gen2XSP =
levels            253 drivers/gpu/drm/radeon/rv730_dpm.c 					  &table->ACPIState.levels[0].vddc);
levels            254 drivers/gpu/drm/radeon/rv730_dpm.c 		table->ACPIState.levels[0].gen2PCIE = 0;
levels            296 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
levels            297 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
levels            298 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
levels            299 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
levels            300 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
levels            302 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
levels            304 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
levels            305 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
levels            306 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
levels            308 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels            310 drivers/gpu/drm/radeon/rv730_dpm.c 	rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
levels            312 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[1] = table->ACPIState.levels[0];
levels            313 drivers/gpu/drm/radeon/rv730_dpm.c 	table->ACPIState.levels[2] = table->ACPIState.levels[0];
levels            326 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
levels            328 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
levels            330 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
levels            332 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
levels            334 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
levels            336 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
levels            338 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
levels            341 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].mclk.mclk730.mclk_value =
levels            344 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels            346 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels            348 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels            350 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
levels            352 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
levels            355 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].sclk.sclk_value =
levels            358 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
levels            360 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].seqValue =
levels            365 drivers/gpu/drm/radeon/rv730_dpm.c 				  &table->initialState.levels[0].vddc);
levels            367 drivers/gpu/drm/radeon/rv730_dpm.c 					  &table->initialState.levels[0].mvdd);
levels            371 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].aT = cpu_to_be32(a_t);
levels            373 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
levels            376 drivers/gpu/drm/radeon/rv730_dpm.c 		table->initialState.levels[0].gen2PCIE = 1;
levels            378 drivers/gpu/drm/radeon/rv730_dpm.c 		table->initialState.levels[0].gen2PCIE = 0;
levels            380 drivers/gpu/drm/radeon/rv730_dpm.c 		table->initialState.levels[0].gen2XSP = 1;
levels            382 drivers/gpu/drm/radeon/rv730_dpm.c 		table->initialState.levels[0].gen2XSP = 0;
levels            384 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[1] = table->initialState.levels[0];
levels            385 drivers/gpu/drm/radeon/rv730_dpm.c 	table->initialState.levels[2] = table->initialState.levels[0];
levels            334 drivers/gpu/drm/radeon/rv740_dpm.c 					  &table->ACPIState.levels[0].vddc);
levels            335 drivers/gpu/drm/radeon/rv740_dpm.c 		table->ACPIState.levels[0].gen2PCIE =
levels            338 drivers/gpu/drm/radeon/rv740_dpm.c 		table->ACPIState.levels[0].gen2XSP =
levels            342 drivers/gpu/drm/radeon/rv740_dpm.c 					  &table->ACPIState.levels[0].vddc);
levels            343 drivers/gpu/drm/radeon/rv740_dpm.c 		table->ACPIState.levels[0].gen2PCIE = 0;
levels            373 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
levels            374 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
levels            375 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
levels            376 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
levels            377 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
levels            378 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
levels            380 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
levels            382 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
levels            383 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
levels            384 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
levels            386 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels            388 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[1] = table->ACPIState.levels[0];
levels            389 drivers/gpu/drm/radeon/rv740_dpm.c 	table->ACPIState.levels[2] = table->ACPIState.levels[0];
levels            391 drivers/gpu/drm/radeon/rv740_dpm.c 	rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
levels            289 drivers/gpu/drm/radeon/rv770_dpm.c 		smc_state->levels[i].aT = cpu_to_be32(a_t);
levels            295 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
levels            309 drivers/gpu/drm/radeon/rv770_dpm.c 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
levels            311 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
levels            685 drivers/gpu/drm/radeon/rv770_dpm.c 					       &smc_state->levels[0],
levels            692 drivers/gpu/drm/radeon/rv770_dpm.c 					       &smc_state->levels[1],
levels            699 drivers/gpu/drm/radeon/rv770_dpm.c 					       &smc_state->levels[2],
levels            704 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
levels            705 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
levels            706 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
levels            708 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[0].seqValue = rv770_get_seq_value(rdev,
levels            710 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[1].seqValue = rv770_get_seq_value(rdev,
levels            712 drivers/gpu/drm/radeon/rv770_dpm.c 	smc_state->levels[2].seqValue = rv770_get_seq_value(rdev,
levels            942 drivers/gpu/drm/radeon/rv770_dpm.c 					  &table->ACPIState.levels[0].vddc);
levels            945 drivers/gpu/drm/radeon/rv770_dpm.c 				table->ACPIState.levels[0].gen2PCIE = 1;
levels            947 drivers/gpu/drm/radeon/rv770_dpm.c 				table->ACPIState.levels[0].gen2PCIE = 0;
levels            949 drivers/gpu/drm/radeon/rv770_dpm.c 			table->ACPIState.levels[0].gen2PCIE = 0;
levels            951 drivers/gpu/drm/radeon/rv770_dpm.c 			table->ACPIState.levels[0].gen2XSP = 1;
levels            953 drivers/gpu/drm/radeon/rv770_dpm.c 			table->ACPIState.levels[0].gen2XSP = 0;
levels            956 drivers/gpu/drm/radeon/rv770_dpm.c 					  &table->ACPIState.levels[0].vddc);
levels            957 drivers/gpu/drm/radeon/rv770_dpm.c 		table->ACPIState.levels[0].gen2PCIE = 0;
levels            981 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
levels            982 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
levels            983 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
levels            984 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
levels            986 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
levels            987 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
levels            989 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
levels            991 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
levels            992 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
levels            993 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
levels            995 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels            997 drivers/gpu/drm/radeon/rv770_dpm.c 	rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
levels            999 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[1] = table->ACPIState.levels[0];
levels           1000 drivers/gpu/drm/radeon/rv770_dpm.c 	table->ACPIState.levels[2] = table->ACPIState.levels[0];
levels           1030 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
levels           1032 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
levels           1034 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
levels           1036 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
levels           1038 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
levels           1040 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
levels           1043 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
levels           1045 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
levels           1048 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].mclk.mclk770.mclk_value =
levels           1051 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           1053 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           1055 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           1057 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
levels           1059 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
levels           1062 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].sclk.sclk_value =
levels           1065 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
levels           1067 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].seqValue =
levels           1072 drivers/gpu/drm/radeon/rv770_dpm.c 				  &table->initialState.levels[0].vddc);
levels           1074 drivers/gpu/drm/radeon/rv770_dpm.c 					  &table->initialState.levels[0].mvdd);
levels           1077 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].aT = cpu_to_be32(a_t);
levels           1079 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
levels           1082 drivers/gpu/drm/radeon/rv770_dpm.c 		table->initialState.levels[0].gen2PCIE = 1;
levels           1084 drivers/gpu/drm/radeon/rv770_dpm.c 		table->initialState.levels[0].gen2PCIE = 0;
levels           1086 drivers/gpu/drm/radeon/rv770_dpm.c 		table->initialState.levels[0].gen2XSP = 1;
levels           1088 drivers/gpu/drm/radeon/rv770_dpm.c 		table->initialState.levels[0].gen2XSP = 0;
levels           1093 drivers/gpu/drm/radeon/rv770_dpm.c 				table->initialState.levels[0].strobeMode =
levels           1096 drivers/gpu/drm/radeon/rv770_dpm.c 				table->initialState.levels[0].strobeMode = 0;
levels           1099 drivers/gpu/drm/radeon/rv770_dpm.c 				table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
levels           1101 drivers/gpu/drm/radeon/rv770_dpm.c 				table->initialState.levels[0].mcFlags =  0;
levels           1105 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[1] = table->initialState.levels[0];
levels           1106 drivers/gpu/drm/radeon/rv770_dpm.c 	table->initialState.levels[2] = table->initialState.levels[0];
levels            135 drivers/gpu/drm/radeon/rv770_smc.h     RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
levels           2318 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[0].dpm2.MaxPS = 0;
levels           2319 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[0].dpm2.NearTDPDec = 0;
levels           2320 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[0].dpm2.AboveSafeInc = 0;
levels           2321 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[0].dpm2.BelowSafeInc = 0;
levels           2322 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
levels           2372 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
levels           2373 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
levels           2374 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
levels           2375 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
levels           2376 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
levels           2432 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
levels           2433 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
levels           3406 drivers/gpu/drm/radeon/si_dpm.c 	u32 levels = ps->performance_level_count;
levels           3409 drivers/gpu/drm/radeon/si_dpm.c 		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
levels           3424 drivers/gpu/drm/radeon/si_dpm.c 		if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
levels           4377 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vDLL_CNTL =
levels           4379 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
levels           4381 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
levels           4383 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
levels           4385 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
levels           4387 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
levels           4389 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
levels           4391 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_SS =
levels           4393 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.vMPLL_SS2 =
levels           4396 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].mclk.mclk_value =
levels           4399 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           4401 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           4403 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           4405 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
levels           4407 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
levels           4409 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
levels           4412 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].sclk.sclk_value =
levels           4415 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].arbRefreshState =
levels           4418 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].ACIndex = 0;
levels           4422 drivers/gpu/drm/radeon/si_dpm.c 					&table->initialState.levels[0].vddc);
levels           4428 drivers/gpu/drm/radeon/si_dpm.c 					       &table->initialState.levels[0].vddc,
levels           4432 drivers/gpu/drm/radeon/si_dpm.c 						      table->initialState.levels[0].vddc.index,
levels           4433 drivers/gpu/drm/radeon/si_dpm.c 						      &table->initialState.levels[0].std_vddc);
levels           4440 drivers/gpu/drm/radeon/si_dpm.c 					  &table->initialState.levels[0].vddci);
levels           4448 drivers/gpu/drm/radeon/si_dpm.c 						 &table->initialState.levels[0].vddc);
levels           4450 drivers/gpu/drm/radeon/si_dpm.c 	si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
levels           4453 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].aT = cpu_to_be32(reg);
levels           4455 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
levels           4457 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
levels           4460 drivers/gpu/drm/radeon/si_dpm.c 		table->initialState.levels[0].strobeMode =
levels           4465 drivers/gpu/drm/radeon/si_dpm.c 			table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
levels           4467 drivers/gpu/drm/radeon/si_dpm.c 			table->initialState.levels[0].mcFlags =  0;
levels           4474 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].dpm2.MaxPS = 0;
levels           4475 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].dpm2.NearTDPDec = 0;
levels           4476 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].dpm2.AboveSafeInc = 0;
levels           4477 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].dpm2.BelowSafeInc = 0;
levels           4478 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
levels           4481 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
levels           4484 drivers/gpu/drm/radeon/si_dpm.c 	table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
levels           4515 drivers/gpu/drm/radeon/si_dpm.c 						pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
levels           4520 drivers/gpu/drm/radeon/si_dpm.c 						       &table->ACPIState.levels[0].vddc, &std_vddc);
levels           4523 drivers/gpu/drm/radeon/si_dpm.c 							      table->ACPIState.levels[0].vddc.index,
levels           4524 drivers/gpu/drm/radeon/si_dpm.c 							      &table->ACPIState.levels[0].std_vddc);
levels           4526 drivers/gpu/drm/radeon/si_dpm.c 		table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
levels           4534 drivers/gpu/drm/radeon/si_dpm.c 							 &table->ACPIState.levels[0].vddc);
levels           4538 drivers/gpu/drm/radeon/si_dpm.c 						pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
levels           4543 drivers/gpu/drm/radeon/si_dpm.c 						       &table->ACPIState.levels[0].vddc, &std_vddc);
levels           4547 drivers/gpu/drm/radeon/si_dpm.c 							      table->ACPIState.levels[0].vddc.index,
levels           4548 drivers/gpu/drm/radeon/si_dpm.c 							      &table->ACPIState.levels[0].std_vddc);
levels           4550 drivers/gpu/drm/radeon/si_dpm.c 		table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
levels           4561 drivers/gpu/drm/radeon/si_dpm.c 							 &table->ACPIState.levels[0].vddc);
levels           4568 drivers/gpu/drm/radeon/si_dpm.c 						  &table->ACPIState.levels[0].vddci);
levels           4579 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vDLL_CNTL =
levels           4581 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
levels           4583 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
levels           4585 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
levels           4587 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
levels           4589 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
levels           4591 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
levels           4593 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_SS =
levels           4595 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.vMPLL_SS2 =
levels           4598 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
levels           4600 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
levels           4602 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
levels           4604 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
levels           4607 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].mclk.mclk_value = 0;
levels           4608 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].sclk.sclk_value = 0;
levels           4610 drivers/gpu/drm/radeon/si_dpm.c 	si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
levels           4613 drivers/gpu/drm/radeon/si_dpm.c 		table->ACPIState.levels[0].ACIndex = 0;
levels           4615 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].dpm2.MaxPS = 0;
levels           4616 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
levels           4617 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
levels           4618 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
levels           4619 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
levels           4622 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
levels           4625 drivers/gpu/drm/radeon/si_dpm.c 	table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
levels           4640 drivers/gpu/drm/radeon/si_dpm.c 					    &state->levels[0]);
levels           4644 drivers/gpu/drm/radeon/si_dpm.c 				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
levels           4646 drivers/gpu/drm/radeon/si_dpm.c 				state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
levels           4650 drivers/gpu/drm/radeon/si_dpm.c 		state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
levels           4651 drivers/gpu/drm/radeon/si_dpm.c 		state->levels[0].ACIndex = 1;
levels           4652 drivers/gpu/drm/radeon/si_dpm.c 		state->levels[0].std_vddc = state->levels[0].vddc;
levels           4971 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
levels           4973 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[ps->performance_level_count - 1].bSP =
levels           5102 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[0].aT = cpu_to_be32(a_t);
levels           5106 drivers/gpu/drm/radeon/si_dpm.c 	smc_state->levels[0].aT = cpu_to_be32(0);
levels           5122 drivers/gpu/drm/radeon/si_dpm.c 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
levels           5124 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].aT = cpu_to_be32(a_t);
levels           5129 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
levels           5222 drivers/gpu/drm/radeon/si_dpm.c 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
levels           5224 drivers/gpu/drm/radeon/si_dpm.c 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
levels           5229 drivers/gpu/drm/radeon/si_dpm.c 						    &smc_state->levels[i]);
levels           5230 drivers/gpu/drm/radeon/si_dpm.c 		smc_state->levels[i].arbRefreshState =
levels           5237 drivers/gpu/drm/radeon/si_dpm.c 			smc_state->levels[i].displayWatermark =
levels           5241 drivers/gpu/drm/radeon/si_dpm.c 			smc_state->levels[i].displayWatermark = (i < 2) ?
levels           5245 drivers/gpu/drm/radeon/si_dpm.c 			smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
levels           5247 drivers/gpu/drm/radeon/si_dpm.c 			smc_state->levels[i].ACIndex = 0;
levels            189 drivers/gpu/drm/radeon/sislands_smc.h     SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
levels            347 drivers/gpu/drm/radeon/sumo_dpm.c 	u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
levels            411 drivers/gpu/drm/radeon/sumo_dpm.c 		m_a = asi * ps->levels[i].sclk / 100;
levels            670 drivers/gpu/drm/radeon/sumo_dpm.c 		pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
levels            762 drivers/gpu/drm/radeon/sumo_dpm.c 		sumo_program_power_level(rdev, &new_ps->levels[i], i);
levels            844 drivers/gpu/drm/radeon/sumo_dpm.c 	if (new_ps->levels[new_ps->num_levels - 1].sclk >=
levels            845 drivers/gpu/drm/radeon/sumo_dpm.c 	    current_ps->levels[current_ps->num_levels - 1].sclk)
levels            862 drivers/gpu/drm/radeon/sumo_dpm.c 	if (new_ps->levels[new_ps->num_levels - 1].sclk <
levels            863 drivers/gpu/drm/radeon/sumo_dpm.c 	    current_ps->levels[current_ps->num_levels - 1].sclk)
levels           1053 drivers/gpu/drm/radeon/sumo_dpm.c 		current_vddc = current_ps->levels[current_index].vddc_index;
levels           1054 drivers/gpu/drm/radeon/sumo_dpm.c 		current_sclk = current_ps->levels[current_index].sclk;
levels           1060 drivers/gpu/drm/radeon/sumo_dpm.c 	ps->levels[0].vddc_index = current_vddc;
levels           1062 drivers/gpu/drm/radeon/sumo_dpm.c 	if (ps->levels[0].sclk > current_sclk)
levels           1063 drivers/gpu/drm/radeon/sumo_dpm.c 		ps->levels[0].sclk = current_sclk;
levels           1065 drivers/gpu/drm/radeon/sumo_dpm.c 	ps->levels[0].ss_divider_index =
levels           1066 drivers/gpu/drm/radeon/sumo_dpm.c 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
levels           1068 drivers/gpu/drm/radeon/sumo_dpm.c 	ps->levels[0].ds_divider_index =
levels           1069 drivers/gpu/drm/radeon/sumo_dpm.c 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
levels           1071 drivers/gpu/drm/radeon/sumo_dpm.c 	if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
levels           1072 drivers/gpu/drm/radeon/sumo_dpm.c 		ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
levels           1074 drivers/gpu/drm/radeon/sumo_dpm.c 	if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
levels           1075 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[0].ss_divider_index > 1)
levels           1076 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
levels           1079 drivers/gpu/drm/radeon/sumo_dpm.c 	if (ps->levels[0].ss_divider_index == 0)
levels           1080 drivers/gpu/drm/radeon/sumo_dpm.c 		ps->levels[0].ds_divider_index = 0;
levels           1082 drivers/gpu/drm/radeon/sumo_dpm.c 	if (ps->levels[0].ds_divider_index == 0)
levels           1083 drivers/gpu/drm/radeon/sumo_dpm.c 		ps->levels[0].ss_divider_index = 0;
levels           1112 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].vddc_index < min_voltage)
levels           1113 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].vddc_index = min_voltage;
levels           1115 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].sclk < min_sclk)
levels           1116 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].sclk =
levels           1119 drivers/gpu/drm/radeon/sumo_dpm.c 		ps->levels[i].ss_divider_index =
levels           1120 drivers/gpu/drm/radeon/sumo_dpm.c 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
levels           1122 drivers/gpu/drm/radeon/sumo_dpm.c 		ps->levels[i].ds_divider_index =
levels           1123 drivers/gpu/drm/radeon/sumo_dpm.c 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
levels           1125 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
levels           1126 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
levels           1128 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
levels           1129 drivers/gpu/drm/radeon/sumo_dpm.c 			if (ps->levels[i].ss_divider_index > 1)
levels           1130 drivers/gpu/drm/radeon/sumo_dpm.c 				ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
levels           1133 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].ss_divider_index == 0)
levels           1134 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].ds_divider_index = 0;
levels           1136 drivers/gpu/drm/radeon/sumo_dpm.c 		if (ps->levels[i].ds_divider_index == 0)
levels           1137 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].ss_divider_index = 0;
levels           1140 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].allow_gnb_slow = 1;
levels           1143 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].allow_gnb_slow = 0;
levels           1145 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].allow_gnb_slow = 0;
levels           1147 drivers/gpu/drm/radeon/sumo_dpm.c 			ps->levels[i].allow_gnb_slow = 1;
levels           1399 drivers/gpu/drm/radeon/sumo_dpm.c 	ps->levels[0] = pi->boot_pl;
levels           1435 drivers/gpu/drm/radeon/sumo_dpm.c 	struct sumo_pl *pl = &ps->levels[index];
levels           1737 drivers/gpu/drm/radeon/sumo_dpm.c 	pi->current_ps.levels[0] = pi->boot_pl;
levels           1804 drivers/gpu/drm/radeon/sumo_dpm.c 		struct sumo_pl *pl = &ps->levels[i];
levels           1832 drivers/gpu/drm/radeon/sumo_dpm.c 		pl = &ps->levels[current_index];
levels           1856 drivers/gpu/drm/radeon/sumo_dpm.c 		pl = &ps->levels[current_index];
levels           1887 drivers/gpu/drm/radeon/sumo_dpm.c 		return requested_state->levels[0].sclk;
levels           1889 drivers/gpu/drm/radeon/sumo_dpm.c 		return requested_state->levels[requested_state->num_levels - 1].sclk;
levels             46 drivers/gpu/drm/radeon/sumo_dpm.h 	struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
levels            850 drivers/gpu/drm/radeon/trinity_dpm.c 		trinity_program_power_level(rdev, &new_ps->levels[i], i);
levels            970 drivers/gpu/drm/radeon/trinity_dpm.c 	if (new_ps->levels[new_ps->num_levels - 1].sclk >=
levels            971 drivers/gpu/drm/radeon/trinity_dpm.c 	    current_ps->levels[current_ps->num_levels - 1].sclk)
levels            984 drivers/gpu/drm/radeon/trinity_dpm.c 	if (new_ps->levels[new_ps->num_levels - 1].sclk <
levels            985 drivers/gpu/drm/radeon/trinity_dpm.c 	    current_ps->levels[current_ps->num_levels - 1].sclk)
levels           1332 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0] = pi->boot_pl;
levels           1355 drivers/gpu/drm/radeon/trinity_dpm.c 	pi->current_ps.levels[0] = pi->boot_pl;
levels           1410 drivers/gpu/drm/radeon/trinity_dpm.c 		current_vddc = current_ps->levels[current_index].vddc_index;
levels           1411 drivers/gpu/drm/radeon/trinity_dpm.c 		current_sclk = current_ps->levels[current_index].sclk;
levels           1417 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].vddc_index = current_vddc;
levels           1419 drivers/gpu/drm/radeon/trinity_dpm.c 	if (ps->levels[0].sclk > current_sclk)
levels           1420 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[0].sclk = current_sclk;
levels           1422 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].ds_divider_index =
levels           1423 drivers/gpu/drm/radeon/trinity_dpm.c 		trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
levels           1424 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index;
levels           1425 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].allow_gnb_slow = 1;
levels           1426 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].force_nbp_state = 0;
levels           1427 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].display_wm = 0;
levels           1428 drivers/gpu/drm/radeon/trinity_dpm.c 	ps->levels[0].vce_wm =
levels           1429 drivers/gpu/drm/radeon/trinity_dpm.c 		trinity_calculate_vce_wm(rdev, ps->levels[0].sclk);
levels           1445 drivers/gpu/drm/radeon/trinity_dpm.c 		else if (ps->levels[index].sclk < 30000)
levels           1564 drivers/gpu/drm/radeon/trinity_dpm.c 		if (ps->levels[i].vddc_index < min_voltage)
levels           1565 drivers/gpu/drm/radeon/trinity_dpm.c 			ps->levels[i].vddc_index = min_voltage;
levels           1567 drivers/gpu/drm/radeon/trinity_dpm.c 		if (ps->levels[i].sclk < min_sclk)
levels           1568 drivers/gpu/drm/radeon/trinity_dpm.c 			ps->levels[i].sclk =
levels           1574 drivers/gpu/drm/radeon/trinity_dpm.c 			if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
levels           1575 drivers/gpu/drm/radeon/trinity_dpm.c 				ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
levels           1578 drivers/gpu/drm/radeon/trinity_dpm.c 			if (ps->levels[i].vddc_index < min_vce_voltage)
levels           1579 drivers/gpu/drm/radeon/trinity_dpm.c 				ps->levels[i].vddc_index = min_vce_voltage;
levels           1582 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[i].ds_divider_index =
levels           1583 drivers/gpu/drm/radeon/trinity_dpm.c 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
levels           1585 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index;
levels           1587 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[i].allow_gnb_slow = 1;
levels           1588 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[i].force_nbp_state = 0;
levels           1589 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[i].display_wm =
levels           1591 drivers/gpu/drm/radeon/trinity_dpm.c 		ps->levels[i].vce_wm =
levels           1592 drivers/gpu/drm/radeon/trinity_dpm.c 			trinity_calculate_vce_wm(rdev, ps->levels[0].sclk);
levels           1615 drivers/gpu/drm/radeon/trinity_dpm.c 			ps->levels[ps->num_levels - 1].allow_gnb_slow = 0;
levels           1714 drivers/gpu/drm/radeon/trinity_dpm.c 	struct trinity_pl *pl = &ps->levels[index];
levels           2022 drivers/gpu/drm/radeon/trinity_dpm.c 		struct trinity_pl *pl = &ps->levels[i];
levels           2044 drivers/gpu/drm/radeon/trinity_dpm.c 		pl = &ps->levels[current_index];
levels           2065 drivers/gpu/drm/radeon/trinity_dpm.c 		pl = &ps->levels[current_index];
levels           2097 drivers/gpu/drm/radeon/trinity_dpm.c 		return requested_state->levels[0].sclk;
levels           2099 drivers/gpu/drm/radeon/trinity_dpm.c 		return requested_state->levels[requested_state->num_levels - 1].sclk;
levels             49 drivers/gpu/drm/radeon/trinity_dpm.h 	struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
levels           2183 drivers/infiniband/hw/bnxt_re/ib_verbs.c 	wqe->frmr.levels = qplib_frpl->hwq.level + 1;
levels           1719 drivers/infiniband/hw/bnxt_re/qplib_fp.c 			((wqe->frmr.levels << SQ_FR_PMR_NUMLEVELS_SFT) &
levels            202 drivers/infiniband/hw/bnxt_re/qplib_fp.h 			u8		levels;
levels           3342 drivers/iommu/amd_iommu.c 	int levels, ret;
levels           3348 drivers/iommu/amd_iommu.c 	for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
levels           3349 drivers/iommu/amd_iommu.c 		levels += 1;
levels           3351 drivers/iommu/amd_iommu.c 	if (levels > amd_iommu_max_glx_val)
levels           3370 drivers/iommu/amd_iommu.c 	domain->glx      = levels;
levels             38 drivers/iommu/io-pgtable-arm.c #define ARM_LPAE_START_LVL(d)		(ARM_LPAE_MAX_LEVELS - (d)->levels)
levels             45 drivers/iommu/io-pgtable-arm.c 	((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1))		\
levels            183 drivers/iommu/io-pgtable-arm.c 	int			levels;
levels            773 drivers/iommu/io-pgtable-arm.c 	data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
levels            776 drivers/iommu/io-pgtable-arm.c 	pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
levels            906 drivers/iommu/io-pgtable-arm.c 	if (data->levels == ARM_LPAE_MAX_LEVELS) {
levels            912 drivers/iommu/io-pgtable-arm.c 			data->levels--;
levels           1037 drivers/iommu/io-pgtable-arm.c 	if (data->levels < ARM_LPAE_MAX_LEVELS) {
levels           1038 drivers/iommu/io-pgtable-arm.c 		data->levels = ARM_LPAE_MAX_LEVELS;
levels           1135 drivers/iommu/io-pgtable-arm.c 		data->levels, data->pgd_size, data->pg_shift,
levels            400 drivers/md/dm-era-target.c 	md->writeset_tree_info.levels = 1;
levels            457 drivers/md/dm-thin-metadata.c 	pmd->info.levels = 2;
levels            468 drivers/md/dm-thin-metadata.c 	pmd->tl_info.levels = 1;
levels            476 drivers/md/dm-thin-metadata.c 	pmd->bl_info.levels = 1;
levels            484 drivers/md/dm-thin-metadata.c 	pmd->details_info.levels = 1;
levels            335 drivers/md/dm-verity-target.c 	if (likely(v->levels)) {
levels            350 drivers/md/dm-verity-target.c 	for (i = v->levels - 1; i >= 0; i--) {
levels            584 drivers/md/dm-verity-target.c 	for (i = v->levels - 2; i >= 0; i--) {
levels           1134 drivers/md/dm-verity-target.c 	v->levels = 0;
levels           1136 drivers/md/dm-verity-target.c 		while (v->hash_per_block_bits * v->levels < 64 &&
levels           1138 drivers/md/dm-verity-target.c 		       (v->hash_per_block_bits * v->levels))
levels           1139 drivers/md/dm-verity-target.c 			v->levels++;
levels           1141 drivers/md/dm-verity-target.c 	if (v->levels > DM_VERITY_MAX_LEVELS) {
levels           1148 drivers/md/dm-verity-target.c 	for (i = v->levels - 1; i >= 0; i--) {
levels             51 drivers/md/dm-verity.h 	unsigned char levels;	/* the number of tree levels */
levels            639 drivers/md/persistent-data/dm-array.c 	info->btree_info.levels = 1;
levels            521 drivers/md/persistent-data/dm-btree-remove.c 	unsigned level, last_level = info->levels - 1;
levels            529 drivers/md/persistent-data/dm-btree-remove.c 	for (level = 0; level < info->levels; level++) {
levels            618 drivers/md/persistent-data/dm-btree-remove.c 	unsigned level, last_level = info->levels - 1;
levels            205 drivers/md/persistent-data/dm-btree.c 	return f->level < (info->levels - 1);
levels            377 drivers/md/persistent-data/dm-btree.c 	unsigned level, last_level = info->levels - 1;
levels            384 drivers/md/persistent-data/dm-btree.c 	for (level = 0; level < info->levels; level++) {
levels            479 drivers/md/persistent-data/dm-btree.c 	for (level = 0; level < info->levels - 1u; level++) {
levels            768 drivers/md/persistent-data/dm-btree.c 	unsigned level, index = -1, last_level = info->levels - 1;
levels            777 drivers/md/persistent-data/dm-btree.c 	for (level = 0; level < (info->levels - 1); level++) {
levels            912 drivers/md/persistent-data/dm-btree.c 	for (level = 0; level < info->levels; level++) {
levels            914 drivers/md/persistent-data/dm-btree.c 			     level == info->levels - 1 ? NULL : &root);
levels            988 drivers/md/persistent-data/dm-btree.c 	BUG_ON(info->levels > 1);
levels             87 drivers/md/persistent-data/dm-btree.h 	unsigned levels;
levels            198 drivers/md/persistent-data/dm-space-map-common.c 	ll->bitmap_info.levels = 1;
levels            211 drivers/md/persistent-data/dm-space-map-common.c 	ll->ref_count_info.levels = 1;
levels           2561 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c 	int levels;
levels           2582 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c 	levels = 2 * FDB_MAX_PRIO * (FDB_MAX_CHAIN + 1);
levels           2585 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c 					  levels);
levels           1148 drivers/platform/x86/dell-laptop.c 	u8 levels;
levels           1222 drivers/platform/x86/dell-laptop.c 	info->levels = (buffer.output[2] >> 16) & 0xFF;
levels           1224 drivers/platform/x86/dell-laptop.c 	if (quirks && quirks->kbd_led_levels_off_1 && info->levels)
levels           1225 drivers/platform/x86/dell-laptop.c 		info->levels--;
levels           1241 drivers/platform/x86/dell-laptop.c 	if (kbd_info.levels != 0)
levels           1242 drivers/platform/x86/dell-laptop.c 		return kbd_info.levels;
levels           1252 drivers/platform/x86/dell-laptop.c 	if (kbd_info.levels != 0)
levels           1267 drivers/platform/x86/dell-laptop.c 	if (kbd_info.levels != 0) {
levels           1528 drivers/platform/x86/dell-laptop.c 	if ((ret == 0 && (kbd_info.levels != 0 || kbd_mode_levels_count >= 2))
levels           1356 drivers/platform/x86/toshiba_acpi.c 	int levels;
levels           1362 drivers/platform/x86/toshiba_acpi.c 	levels = dev->backlight_dev->props.max_brightness + 1;
levels           1370 drivers/platform/x86/toshiba_acpi.c 	seq_printf(m, "brightness_levels:       %d\n", levels);
levels           1416 drivers/platform/x86/toshiba_acpi.c 	int levels;
levels           1424 drivers/platform/x86/toshiba_acpi.c 	levels = dev->backlight_dev->props.max_brightness + 1;
levels           1426 drivers/platform/x86/toshiba_acpi.c 	    value < 0 && value > levels)
levels             60 drivers/thermal/intel/int340x_thermal/int3406_thermal.c 	acpi_level = d->br->levels[d->upper_limit - state];
levels             83 drivers/thermal/intel/int340x_thermal/int3406_thermal.c 		if (acpi_level <= d->br->levels[index])
levels            115 drivers/thermal/intel/int340x_thermal/int3406_thermal.c 		d->lower_limit = int3406_thermal_get_index(d->br->levels,
levels            120 drivers/thermal/intel/int340x_thermal/int3406_thermal.c 		d->upper_limit = int3406_thermal_get_index(d->br->levels,
levels            611 drivers/vfio/vfio_iommu_spapr_tce.c 			__u32 levels,
levels            617 drivers/vfio/vfio_iommu_spapr_tce.c 			levels);
levels            626 drivers/vfio/vfio_iommu_spapr_tce.c 			page_shift, window_size, levels, ptbl);
levels            644 drivers/vfio/vfio_iommu_spapr_tce.c 		__u32 page_shift, __u64 window_size, __u32 levels,
levels            673 drivers/vfio/vfio_iommu_spapr_tce.c 			page_shift, window_size, levels, &tbl);
levels            842 drivers/vfio/vfio_iommu_spapr_tce.c 			info.ddw.levels = table_group->max_levels;
levels           1088 drivers/vfio/vfio_iommu_spapr_tce.c 					create.window_size, create.levels,
levels             27 drivers/video/backlight/pwm_bl.c 	unsigned int		*levels;
levels             98 drivers/video/backlight/pwm_bl.c 	if (pb->levels)
levels             99 drivers/video/backlight/pwm_bl.c 		duty_cycle = pb->levels[brightness];
levels            203 drivers/video/backlight/pwm_bl.c 	data->levels = devm_kcalloc(dev, data->max_brightness,
levels            204 drivers/video/backlight/pwm_bl.c 				    sizeof(*data->levels), GFP_KERNEL);
levels            205 drivers/video/backlight/pwm_bl.c 	if (!data->levels)
levels            216 drivers/video/backlight/pwm_bl.c 		data->levels[i] = (unsigned int)retval;
levels            265 drivers/video/backlight/pwm_bl.c 		size_t size = sizeof(*data->levels) * data->max_brightness;
levels            268 drivers/video/backlight/pwm_bl.c 		data->levels = devm_kzalloc(dev, size, GFP_KERNEL);
levels            269 drivers/video/backlight/pwm_bl.c 		if (!data->levels)
levels            273 drivers/video/backlight/pwm_bl.c 						 data->levels,
levels            310 drivers/video/backlight/pwm_bl.c 				if ((data->levels[i + 1] - data->levels[i]) /
levels            332 drivers/video/backlight/pwm_bl.c 				value = data->levels[i];
levels            333 drivers/video/backlight/pwm_bl.c 				n = (data->levels[i + 1] - value) / num_steps;
levels            341 drivers/video/backlight/pwm_bl.c 					table[levels_count] = data->levels[i];
levels            345 drivers/video/backlight/pwm_bl.c 			table[levels_count] = data->levels[i];
levels            352 drivers/video/backlight/pwm_bl.c 			devm_kfree(dev, data->levels);
levels            353 drivers/video/backlight/pwm_bl.c 			data->levels = table;
levels            393 drivers/video/backlight/pwm_bl.c 	unsigned int min_val = data->levels[0];
levels            394 drivers/video/backlight/pwm_bl.c 	unsigned int max_val = data->levels[nlevels - 1];
levels            406 drivers/video/backlight/pwm_bl.c 		unsigned int delta = abs(linear_value - data->levels[i]);
levels            566 drivers/video/backlight/pwm_bl.c 	if (data->levels) {
levels            573 drivers/video/backlight/pwm_bl.c 			if (data->levels[i] > pb->scale)
levels            574 drivers/video/backlight/pwm_bl.c 				pb->scale = data->levels[i];
levels            576 drivers/video/backlight/pwm_bl.c 			pb->levels = data->levels;
levels            604 drivers/video/backlight/pwm_bl.c 			if (data->levels[i] > pb->scale)
levels            605 drivers/video/backlight/pwm_bl.c 				pb->scale = data->levels[i];
levels            607 drivers/video/backlight/pwm_bl.c 			pb->levels = data->levels;
levels             43 drivers/xen/xenbus/xenbus.h 	unsigned int levels;
levels            577 drivers/xen/xenbus/xenbus_probe.c 	rootlen = strsep_len(node, '/', bus->levels);
levels            191 drivers/xen/xenbus/xenbus_probe_backend.c 	.levels = 3,		/* backend/type/<frontend>/<id> */
levels            139 drivers/xen/xenbus/xenbus_probe_frontend.c 	.levels = 2,		/* device/type/<id> */
levels            706 fs/ext4/namei.c 			     struct dx_entry *entries, int levels)
levels            719 fs/ext4/namei.c 		printk("%s%3u:%03u hash %8x/%8x ",levels?"":"   ", i, block, hash, range);
levels            723 fs/ext4/namei.c 		stats = levels?
levels            724 fs/ext4/namei.c 		   dx_show_entries(hinfo, dir, ((struct dx_node *) bh->b_data)->entries, levels - 1):
levels            734 fs/ext4/namei.c 		       levels ? "" : "   ", names, space/bcount,
levels           2314 fs/ext4/namei.c 		int levels = frame - frames + 1;
levels           2332 fs/ext4/namei.c 		if (add_level && levels == ext4_dir_htree_level(sb)) {
levels           2335 fs/ext4/namei.c 					 dir->i_ino, levels);
levels            218 fs/qnx6/inode.c 	pr_debug("inode_levels: %02x\n", sb->Inode.levels);
levels            419 fs/qnx6/inode.c 	if (sb1->Inode.levels > QNX6_PTR_MAX_LEVELS) {
levels            421 fs/qnx6/inode.c 		       QNX6_PTR_MAX_LEVELS, sb1->Inode.levels);
levels            424 fs/qnx6/inode.c 	if (sb1->Longfile.levels > QNX6_PTR_MAX_LEVELS) {
levels            426 fs/qnx6/inode.c 		       QNX6_PTR_MAX_LEVELS, sb1->Longfile.levels);
levels            515 fs/qnx6/inode.c 		ei->di_filelevels = p->levels;
levels             17 include/acpi/video.h 	int *levels;
levels             16 include/linux/pwm_backlight.h 	unsigned int *levels;
levels             89 include/linux/qnx6_fs.h 	__u8		levels;
levels            960 include/uapi/linux/soundcard.h   int levels[32];
levels            813 include/uapi/linux/vfio.h 	__u32 levels;
levels            925 include/uapi/linux/vfio.h 	__u32 levels;
levels            364 kernel/power/snapshot.c 	int levels;			/* Number of Radix Tree Levels */
levels            445 kernel/power/snapshot.c 	for (i = zone->levels; i < levels_needed; i++) {
levels            453 kernel/power/snapshot.c 		zone->levels += 1;
levels            465 kernel/power/snapshot.c 	for (i = zone->levels; i > 0; i--) {
levels            751 kernel/power/snapshot.c 	for (i = zone->levels; i > 0; i--) {
levels           1462 kernel/time/timer.c 	int i, levels = 0;
levels           1471 kernel/time/timer.c 			levels++;
levels           1479 kernel/time/timer.c 	return levels;
levels           1743 kernel/time/timer.c 	int levels;
levels           1769 kernel/time/timer.c 		levels = collect_expired_timers(base, heads);
levels           1772 kernel/time/timer.c 		while (levels--)
levels           1773 kernel/time/timer.c 			expire_timers(base, heads + levels);
levels            907 sound/pci/lx6464es/lx6464es.c 	u32 levels[64];
levels            913 sound/pci/lx6464es/lx6464es.c 	err = lx_level_peaks(chip, 1, 64, levels);
levels            919 sound/pci/lx6464es/lx6464es.c 			snd_iprintf(buffer, "%08x ", levels[i*8+j]);
levels            925 sound/pci/lx6464es/lx6464es.c 	err = lx_level_peaks(chip, 0, 64, levels);
levels            931 sound/pci/lx6464es/lx6464es.c 			snd_iprintf(buffer, "%08x ", levels[i*8+j]);
levels           6169 sound/pci/rme9652/hdspm.c 	struct hdspm_peak_rms *levels;
levels           6178 sound/pci/rme9652/hdspm.c 		levels = &hdspm->peak_rms;
levels           6180 sound/pci/rme9652/hdspm.c 			levels->input_peaks[i] =
levels           6183 sound/pci/rme9652/hdspm.c 			levels->playback_peaks[i] =
levels           6186 sound/pci/rme9652/hdspm.c 			levels->output_peaks[i] =
levels           6190 sound/pci/rme9652/hdspm.c 			levels->input_rms[i] =
levels           6195 sound/pci/rme9652/hdspm.c 			levels->playback_rms[i] =
levels           6200 sound/pci/rme9652/hdspm.c 			levels->output_rms[i] =
levels           6208 sound/pci/rme9652/hdspm.c 			levels->speed = qs;
levels           6210 sound/pci/rme9652/hdspm.c 			levels->speed = ds;
levels           6212 sound/pci/rme9652/hdspm.c 			levels->speed = ss;
levels           6214 sound/pci/rme9652/hdspm.c 		levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
levels           6216 sound/pci/rme9652/hdspm.c 		s = copy_to_user(argp, levels, sizeof(*levels));
levels            911 sound/usb/mixer_scarlett_gen2.c 					  u16 *levels)
levels            931 sound/usb/mixer_scarlett_gen2.c 		levels[i] = resp[i];
levels            707 tools/power/x86/intel-speed-select/isst-config.c _get_tdp_level("get-config-levels", levels, levels, "TDP levels");
levels            708 tools/power/x86/intel-speed-select/isst-config.c _get_tdp_level("get-config-version", levels, version, "TDP version");
levels            709 tools/power/x86/intel-speed-select/isst-config.c _get_tdp_level("get-config-enabled", levels, enabled, "TDP enable status");
levels            710 tools/power/x86/intel-speed-select/isst-config.c _get_tdp_level("get-config-current_level", levels, current_level,
levels            712 tools/power/x86/intel-speed-select/isst-config.c _get_tdp_level("get-lock-status", levels, locked, "TDP lock status");
levels             22 tools/power/x86/intel-speed-select/isst-core.c 	pkg_dev->levels = (resp >> 8) & 0xff;
levels            521 tools/power/x86/intel-speed-select/isst-core.c 	for (i = 0; i < pkg_dev->levels; ++i) {
levels            544 tools/power/x86/intel-speed-select/isst-core.c 		     pkg_dev->levels);
levels            546 tools/power/x86/intel-speed-select/isst-core.c 	for (i = 0; i <= pkg_dev->levels; ++i) {
levels            320 tools/power/x86/intel-speed-select/isst-display.c 	for (i = 0; i <= pkg_dev->levels; ++i) {
levels            156 tools/power/x86/intel-speed-select/isst.h 	int levels;
levels             67 tools/usb/ffs-test.c 		static const char levels[8][6] = {
levels             79 tools/usb/ffs-test.c 		fprintf(stderr, "%s: %s ", argv0, levels[level]);