level_change_req  486 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 	struct dm_pp_power_level_change_request *level_change_req)
level_change_req  400 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	struct dm_pp_power_level_change_request level_change_req;
level_change_req  407 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
level_change_req  409 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
level_change_req  410 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
level_change_req  411 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
level_change_req  412 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
level_change_req  253 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	struct dm_pp_power_level_change_request level_change_req;
level_change_req  260 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
level_change_req  262 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
level_change_req  263 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
level_change_req  264 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
level_change_req  265 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
level_change_req  198 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dm_pp_power_level_change_request level_change_req;
level_change_req  205 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
level_change_req  207 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
level_change_req  208 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
level_change_req  209 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
level_change_req  210 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
level_change_req  673 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dm_pp_power_level_change_request level_change_req;
level_change_req  680 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
level_change_req  682 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
level_change_req  683 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
level_change_req  684 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
level_change_req  685 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
level_change_req  700 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dm_pp_power_level_change_request level_change_req;
level_change_req  707 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
level_change_req  709 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
level_change_req  710 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
level_change_req  711 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
level_change_req  712 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
level_change_req  727 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dm_pp_power_level_change_request level_change_req;
level_change_req  734 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
level_change_req  736 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
level_change_req  737 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
level_change_req  738 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
level_change_req  739 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
level_change_req  237 drivers/gpu/drm/amd/display/dc/dm_services.h 	struct dm_pp_power_level_change_request *level_change_req);