level0 178 arch/powerpc/platforms/chrp/setup.c u8 level0, type0, active; level0 183 arch/powerpc/platforms/chrp/setup.c level0 = sio_read(0x70); level0 185 arch/powerpc/platforms/chrp/setup.c if (level0 != level || type0 != type || !active) { level0 188 arch/powerpc/platforms/chrp/setup.c name, level0, type0, !active ? "in" : "", level, type); level0 93 drivers/irqchip/irq-sirfsoc.c u32 level0; level0 105 drivers/irqchip/irq-sirfsoc.c sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); level0 117 drivers/irqchip/irq-sirfsoc.c writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); level0 842 virt/kvm/arm/vgic/vgic-mmio-v3.c int level0; level0 849 virt/kvm/arm/vgic/vgic-mmio-v3.c level0 = MPIDR_AFFINITY_LEVEL(affinity, 0); level0 857 virt/kvm/arm/vgic/vgic-mmio-v3.c if (!(sgi_cpu_mask & BIT(level0))) level0 860 virt/kvm/arm/vgic/vgic-mmio-v3.c return level0; level0 922 virt/kvm/arm/vgic/vgic-mmio-v3.c int level0; level0 924 virt/kvm/arm/vgic/vgic-mmio-v3.c level0 = match_mpidr(mpidr, target_cpus, c_vcpu); level0 925 virt/kvm/arm/vgic/vgic-mmio-v3.c if (level0 == -1) level0 929 virt/kvm/arm/vgic/vgic-mmio-v3.c target_cpus &= ~BIT(level0);