lbr_tos 5134 arch/x86/events/intel/core.c if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) lbr_tos 240 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_tos, tos); lbr_tos 384 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_tos, tos); lbr_tos 1173 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1187 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1207 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1226 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1241 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1271 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1285 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 1303 arch/x86/events/intel/lbr.c x86_pmu.lbr_tos = MSR_LBR_TOS; lbr_tos 674 arch/x86/events/perf_event.h unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */