lbr_to 5138 arch/x86/events/intel/core.c check_msr(x86_pmu.lbr_to + i, 0xffffUL))) lbr_to 211 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_to + i, 0); lbr_to 319 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_to + idx, val); lbr_to 335 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_to + idx, val); lbr_to 370 arch/x86/events/intel/lbr.c wrlbr_to (lbr_idx, task_ctx->lbr_to[i]); lbr_to 408 arch/x86/events/intel/lbr.c task_ctx->lbr_to[i] = rdlbr_to(lbr_idx); lbr_to 1175 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_CORE_TO; lbr_to 1189 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_NHM_TO; lbr_to 1209 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_NHM_TO; lbr_to 1228 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_NHM_TO; lbr_to 1243 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_NHM_TO; lbr_to 1273 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_CORE_TO; lbr_to 1287 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_CORE_TO; lbr_to 1305 arch/x86/events/intel/lbr.c x86_pmu.lbr_to = MSR_LBR_NHM_TO; lbr_to 674 arch/x86/events/perf_event.h unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ lbr_to 712 arch/x86/events/perf_event.h u64 lbr_to[MAX_LBR_ENTRIES];