lbr_from 4061 arch/x86/events/intel/core.c unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; lbr_from 4063 arch/x86/events/intel/core.c return x86_pmu.lbr_from <= msr && msr < lbr_from_nr; lbr_from 5137 arch/x86/events/intel/core.c if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && lbr_from 202 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + i, 0); lbr_from 210 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + i, 0); lbr_from 314 arch/x86/events/intel/lbr.c wrmsrl(x86_pmu.lbr_from + idx, val); lbr_from 326 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_from + idx, val); lbr_from 369 arch/x86/events/intel/lbr.c wrlbr_from(lbr_idx, task_ctx->lbr_from[i]); lbr_from 407 arch/x86/events/intel/lbr.c task_ctx->lbr_from[i] = from; lbr_from 552 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); lbr_from 1174 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_CORE_FROM; lbr_from 1188 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_NHM_FROM; lbr_from 1208 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_NHM_FROM; lbr_from 1227 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_NHM_FROM; lbr_from 1242 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_NHM_FROM; lbr_from 1272 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_CORE_FROM; lbr_from 1286 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_CORE_FROM; lbr_from 1304 arch/x86/events/intel/lbr.c x86_pmu.lbr_from = MSR_LBR_NHM_FROM; lbr_from 674 arch/x86/events/perf_event.h unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ lbr_from 711 arch/x86/events/perf_event.h u64 lbr_from[MAX_LBR_ENTRIES];