lb_partitions     985 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions     995 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (lb_partitions <= (wm->vtaps + 1))
lb_partitions    1011 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions    1021 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (lb_partitions <= (wm->vtaps + 1))
lb_partitions     784 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions     794 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (lb_partitions <= (wm->vtaps + 1))
lb_partitions     920 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions     930 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (lb_partitions <= (wm->vtaps + 1))
lb_partitions     459 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 					i, bw_fixed_to_int(data->lb_partitions[i]));
lb_partitions     558 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));
lb_partitions     566 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->lb_partitions[i] = bw_min2(data->lb_partitions_max[i], data->lb_partitions[i]);
lb_partitions     567 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {
lb_partitions     810 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {
lb_partitions    1304 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(2)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
lb_partitions    1306 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
lb_partitions    1929 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i]))));
lb_partitions     413 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	struct bw_fixed lb_partitions[maximum_number_of_surfaces];
lb_partitions    9215 drivers/gpu/drm/radeon/cik.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions    9225 drivers/gpu/drm/radeon/cik.c 		if (lb_partitions <= (wm->vtaps + 1))
lb_partitions    2128 drivers/gpu/drm/radeon/evergreen.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions    2138 drivers/gpu/drm/radeon/evergreen.c 		if (lb_partitions <= (wm->vtaps + 1))
lb_partitions    2274 drivers/gpu/drm/radeon/si.c 	u32 lb_partitions = wm->lb_size / wm->src_width;
lb_partitions    2284 drivers/gpu/drm/radeon/si.c 		if (lb_partitions <= (wm->vtaps + 1))