lb_params 401 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c switch (pipe->plane_res.scl_data.lb_params.depth) { lb_params 983 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); lb_params 447 drivers/gpu/drm/amd/display/dc/core/dc.c pipes->plane_res.scl_data.lb_params.depth, lb_params 988 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; lb_params 1015 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; lb_params 399 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en); lb_params 906 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->lb_params.depth, lb_params 1248 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.depth, lb_params 1419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; lb_params 2128 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; lb_params 2507 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; lb_params 203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c const struct line_buffer_params *lb_params, lb_params 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth); lb_params 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth; lb_params 214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */ lb_params 218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ lb_params 219 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ lb_params 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ lb_params 226 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ lb_params 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth); lb_params 459 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (scl_data->lb_params.alpha_en lb_params 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); lb_params 707 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); lb_params 2272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; lb_params 2273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; lb_params 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->lb_params.alpha_en lb_params 181 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h struct line_buffer_params lb_params; lb_params 1011 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c struct mlxsw_sp_rif_params_ipip_lb lb_params; lb_params 1016 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c lb_params = (struct mlxsw_sp_rif_params_ipip_lb) { lb_params 1022 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c rif = mlxsw_sp_rif_create(mlxsw_sp, &lb_params.common, extack);