lb_bpc            400 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 		DC_LOG_BANDWIDTH_CALCS("	[uint32_t] lb_bpc[%d]:%d", i, data->lb_bpc[i]);
lb_bpc            272 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->lb_bpc[0] = data->underlay_lb_bpc;
lb_bpc            273 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->lb_bpc[1] = data->underlay_lb_bpc;
lb_bpc            274 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->lb_bpc[2] = data->underlay_lb_bpc;
lb_bpc            275 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->lb_bpc[3] = data->underlay_lb_bpc;
lb_bpc            331 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->lb_bpc[i] = data->graphics_lb_bpc;
lb_bpc            375 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->lb_bpc[maximum_number_of_surfaces - 2] = 8;
lb_bpc            376 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->lb_bpc[maximum_number_of_surfaces - 1] = 8;
lb_bpc            547 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			switch (data->lb_bpc[i]) {
lb_bpc            555 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->lb_line_pitch = bw_ceil2(bw_mul(bw_int_to_fixed(data->lb_bpc[i]), data->source_width_in_lb), bw_int_to_fixed(48));
lb_bpc           1209 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 							switch (data->lb_bpc[i]) {
lb_bpc           1228 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 							switch (data->lb_bpc[i]) {
lb_bpc           1302 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) {
lb_bpc           1660 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				switch (data->lb_bpc[i]) {
lb_bpc           1679 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				switch (data->lb_bpc[i]) {
lb_bpc            418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
lb_bpc            432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
lb_bpc            433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
lb_bpc            434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 	memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
lb_bpc            376 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	uint32_t lb_bpc[maximum_number_of_surfaces];