layers 375 arch/parisc/include/uapi/asm/pdc.h unsigned int layers[6];/* device-specific layer-info */ layers 624 arch/parisc/include/uapi/asm/pdc.h unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ layers 1042 arch/parisc/kernel/drivers.c mod_path.layers[0], mod_path.layers[1], mod_path.layers[2], layers 1043 arch/parisc/kernel/drivers.c mod_path.layers[3], mod_path.layers[4], mod_path.layers[5]); layers 1253 arch/parisc/kernel/firmware.c PAGE0->mem_cons.spa, __pa(PAGE0->mem_cons.dp.layers), layers 1281 arch/parisc/kernel/firmware.c PAGE0->mem_kbd.spa, __pa(PAGE0->mem_kbd.dp.layers), layers 282 drivers/edac/altera_edac.c struct edac_mc_layer layers[2]; layers 358 drivers/edac/altera_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 359 drivers/edac/altera_edac.c layers[0].size = 1; layers 360 drivers/edac/altera_edac.c layers[0].is_virt_csrow = true; layers 361 drivers/edac/altera_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 362 drivers/edac/altera_edac.c layers[1].size = 1; layers 363 drivers/edac/altera_edac.c layers[1].is_virt_csrow = false; layers 364 drivers/edac/altera_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, layers 3427 drivers/edac/amd64_edac.c struct edac_mc_layer layers[2]; layers 3476 drivers/edac/amd64_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 3477 drivers/edac/amd64_edac.c layers[0].size = pvt->csels[0].b_cnt; layers 3478 drivers/edac/amd64_edac.c layers[0].is_virt_csrow = true; layers 3479 drivers/edac/amd64_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 3490 drivers/edac/amd64_edac.c layers[1].size = num_umcs; layers 3492 drivers/edac/amd64_edac.c layers[1].size = 2; layers 3493 drivers/edac/amd64_edac.c layers[1].is_virt_csrow = false; layers 3495 drivers/edac/amd64_edac.c mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0); layers 238 drivers/edac/amd76x_edac.c struct edac_mc_layer layers[2]; layers 247 drivers/edac/amd76x_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 248 drivers/edac/amd76x_edac.c layers[0].size = AMD76X_NR_CSROWS; layers 249 drivers/edac/amd76x_edac.c layers[0].is_virt_csrow = true; layers 250 drivers/edac/amd76x_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 251 drivers/edac/amd76x_edac.c layers[1].size = 1; layers 252 drivers/edac/amd76x_edac.c layers[1].is_virt_csrow = false; layers 253 drivers/edac/amd76x_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 286 drivers/edac/armada_xp_edac.c struct edac_mc_layer layers[1]; layers 311 drivers/edac/armada_xp_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 312 drivers/edac/armada_xp_edac.c layers[0].size = SDRAM_NUM_CS; layers 313 drivers/edac/armada_xp_edac.c layers[0].is_virt_csrow = true; layers 315 drivers/edac/armada_xp_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*drvdata)); layers 282 drivers/edac/aspeed_edac.c struct edac_mc_layer layers[2]; layers 312 drivers/edac/aspeed_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 313 drivers/edac/aspeed_edac.c layers[0].size = 1; layers 314 drivers/edac/aspeed_edac.c layers[0].is_virt_csrow = true; layers 315 drivers/edac/aspeed_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 316 drivers/edac/aspeed_edac.c layers[1].size = 1; layers 317 drivers/edac/aspeed_edac.c layers[1].is_virt_csrow = false; layers 319 drivers/edac/aspeed_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 246 drivers/edac/bluefield_edac.c struct edac_mc_layer layers[1]; layers 273 drivers/edac/bluefield_edac.c layers[0].type = EDAC_MC_LAYER_SLOT; layers 274 drivers/edac/bluefield_edac.c layers[0].size = dimm_count; layers 275 drivers/edac/bluefield_edac.c layers[0].is_virt_csrow = true; layers 277 drivers/edac/bluefield_edac.c mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv)); layers 172 drivers/edac/cell_edac.c struct edac_mc_layer layers[2]; layers 202 drivers/edac/cell_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 203 drivers/edac/cell_edac.c layers[0].size = 1; layers 204 drivers/edac/cell_edac.c layers[0].is_virt_csrow = true; layers 205 drivers/edac/cell_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 206 drivers/edac/cell_edac.c layers[1].size = num_chans; layers 207 drivers/edac/cell_edac.c layers[1].is_virt_csrow = false; layers 208 drivers/edac/cell_edac.c mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, layers 910 drivers/edac/cpc925_edac.c struct edac_mc_layer layers[2]; layers 948 drivers/edac/cpc925_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 949 drivers/edac/cpc925_edac.c layers[0].size = CPC925_NR_CSROWS; layers 950 drivers/edac/cpc925_edac.c layers[0].is_virt_csrow = true; layers 951 drivers/edac/cpc925_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 952 drivers/edac/cpc925_edac.c layers[1].size = nr_channels; layers 953 drivers/edac/cpc925_edac.c layers[1].is_virt_csrow = false; layers 954 drivers/edac/cpc925_edac.c mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, layers 65 drivers/edac/debugfs.c edac_layer_name[mci->layers[i].type]); layers 1261 drivers/edac/e752x_edac.c struct edac_mc_layer layers[2]; layers 1288 drivers/edac/e752x_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 1289 drivers/edac/e752x_edac.c layers[0].size = E752X_NR_CSROWS; layers 1290 drivers/edac/e752x_edac.c layers[0].is_virt_csrow = true; layers 1291 drivers/edac/e752x_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 1292 drivers/edac/e752x_edac.c layers[1].size = drc_chan + 1; layers 1293 drivers/edac/e752x_edac.c layers[1].is_virt_csrow = false; layers 1294 drivers/edac/e752x_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 425 drivers/edac/e7xxx_edac.c struct edac_mc_layer layers[2]; layers 444 drivers/edac/e7xxx_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 445 drivers/edac/e7xxx_edac.c layers[0].size = E7XXX_NR_CSROWS; layers 446 drivers/edac/e7xxx_edac.c layers[0].is_virt_csrow = true; layers 447 drivers/edac/e7xxx_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 448 drivers/edac/e7xxx_edac.c layers[1].size = drc_chan + 1; layers 449 drivers/edac/e7xxx_edac.c layers[1].is_virt_csrow = false; layers 450 drivers/edac/e7xxx_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 126 drivers/edac/edac_mc.c edac_layer_name[mci->layers[i].type], layers 307 drivers/edac/edac_mc.c struct edac_mc_layer *layers, layers 329 drivers/edac/edac_mc.c tot_dimms *= layers[i].size; layers 330 drivers/edac/edac_mc.c if (layers[i].is_virt_csrow) layers 331 drivers/edac/edac_mc.c tot_csrows *= layers[i].size; layers 333 drivers/edac/edac_mc.c tot_channels *= layers[i].size; layers 335 drivers/edac/edac_mc.c if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) layers 347 drivers/edac/edac_mc.c count *= layers[i].size; layers 383 drivers/edac/edac_mc.c mci->layers = layer; layers 384 drivers/edac/edac_mc.c memcpy(mci->layers, layers, sizeof(*layer) * n_layers); layers 452 drivers/edac/edac_mc.c edac_layer_name[layers[j].type], layers 468 drivers/edac/edac_mc.c if (layers[0].is_virt_csrow) { layers 485 drivers/edac/edac_mc.c if (pos[j] < layers[j].size) layers 923 drivers/edac/edac_mc.c index *= mci->layers[i + 1].size; layers 948 drivers/edac/edac_mc.c index *= mci->layers[i + 1].size; layers 1115 drivers/edac/edac_mc.c if (pos[i] >= (int)mci->layers[i].size) { layers 1119 drivers/edac/edac_mc.c edac_layer_name[mci->layers[i].type], layers 1120 drivers/edac/edac_mc.c pos[i], mci->layers[i].size); layers 1225 drivers/edac/edac_mc.c edac_layer_name[mci->layers[i].type], layers 127 drivers/edac/edac_mc.h struct edac_mc_layer *layers, layers 558 drivers/edac/edac_mc_sysfs.c off = EDAC_DIMM_OFF(dimm->mci->layers, layers 575 drivers/edac/edac_mc_sysfs.c off = EDAC_DIMM_OFF(dimm->mci->layers, layers 693 drivers/edac/edac_mc_sysfs.c cnt *= mci->layers[i].size; layers 836 drivers/edac/edac_mc_sysfs.c edac_layer_name[mci->layers[i].type], layers 837 drivers/edac/edac_mc_sysfs.c mci->layers[i].size - 1); layers 479 drivers/edac/fsl_ddr_edac.c struct edac_mc_layer layers[2]; layers 488 drivers/edac/fsl_ddr_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 489 drivers/edac/fsl_ddr_edac.c layers[0].size = 4; layers 490 drivers/edac/fsl_ddr_edac.c layers[0].is_virt_csrow = true; layers 491 drivers/edac/fsl_ddr_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 492 drivers/edac/fsl_ddr_edac.c layers[1].size = 1; layers 493 drivers/edac/fsl_ddr_edac.c layers[1].is_virt_csrow = false; layers 494 drivers/edac/fsl_ddr_edac.c mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, layers 109 drivers/edac/ghes_edac.c struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 480 drivers/edac/ghes_edac.c struct edac_mc_layer layers[1]; layers 512 drivers/edac/ghes_edac.c layers[0].type = EDAC_MC_LAYER_ALL_MEM; layers 513 drivers/edac/ghes_edac.c layers[0].size = num_dimm; layers 514 drivers/edac/ghes_edac.c layers[0].is_virt_csrow = true; layers 516 drivers/edac/ghes_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt)); layers 553 drivers/edac/ghes_edac.c struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 148 drivers/edac/highbank_mc_edac.c struct edac_mc_layer layers[2]; layers 162 drivers/edac/highbank_mc_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 163 drivers/edac/highbank_mc_edac.c layers[0].size = 1; layers 164 drivers/edac/highbank_mc_edac.c layers[0].is_virt_csrow = true; layers 165 drivers/edac/highbank_mc_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 166 drivers/edac/highbank_mc_edac.c layers[1].size = 1; layers 167 drivers/edac/highbank_mc_edac.c layers[1].is_virt_csrow = false; layers 168 drivers/edac/highbank_mc_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, layers 157 drivers/edac/i10nm_base.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 314 drivers/edac/i3000_edac.c struct edac_mc_layer layers[2]; layers 357 drivers/edac/i3000_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 358 drivers/edac/i3000_edac.c layers[0].size = I3000_RANKS / nr_channels; layers 359 drivers/edac/i3000_edac.c layers[0].is_virt_csrow = true; layers 360 drivers/edac/i3000_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 361 drivers/edac/i3000_edac.c layers[1].size = nr_channels; layers 362 drivers/edac/i3000_edac.c layers[1].is_virt_csrow = false; layers 363 drivers/edac/i3000_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 341 drivers/edac/i3200_edac.c struct edac_mc_layer layers[2]; layers 356 drivers/edac/i3200_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 357 drivers/edac/i3200_edac.c layers[0].size = I3200_DIMMS; layers 358 drivers/edac/i3200_edac.c layers[0].is_virt_csrow = true; layers 359 drivers/edac/i3200_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 360 drivers/edac/i3200_edac.c layers[1].size = nr_channels; layers 361 drivers/edac/i3200_edac.c layers[1].is_virt_csrow = false; layers 362 drivers/edac/i3200_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, layers 395 drivers/edac/i3200_edac.c struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 1278 drivers/edac/i5000_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, layers 1358 drivers/edac/i5000_edac.c struct edac_mc_layer layers[3]; layers 1392 drivers/edac/i5000_edac.c layers[0].type = EDAC_MC_LAYER_BRANCH; layers 1393 drivers/edac/i5000_edac.c layers[0].size = MAX_BRANCHES; layers 1394 drivers/edac/i5000_edac.c layers[0].is_virt_csrow = false; layers 1395 drivers/edac/i5000_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 1396 drivers/edac/i5000_edac.c layers[1].size = num_channels / MAX_BRANCHES; layers 1397 drivers/edac/i5000_edac.c layers[1].is_virt_csrow = false; layers 1398 drivers/edac/i5000_edac.c layers[2].type = EDAC_MC_LAYER_SLOT; layers 1399 drivers/edac/i5000_edac.c layers[2].size = num_dimms_per_channel; layers 1400 drivers/edac/i5000_edac.c layers[2].is_virt_csrow = true; layers 1401 drivers/edac/i5000_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 863 drivers/edac/i5100_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, layers 997 drivers/edac/i5100_edac.c struct edac_mc_layer layers[2]; layers 1058 drivers/edac/i5100_edac.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 1059 drivers/edac/i5100_edac.c layers[0].size = 2; layers 1060 drivers/edac/i5100_edac.c layers[0].is_virt_csrow = false; layers 1061 drivers/edac/i5100_edac.c layers[1].type = EDAC_MC_LAYER_SLOT; layers 1062 drivers/edac/i5100_edac.c layers[1].size = ranksperch; layers 1063 drivers/edac/i5100_edac.c layers[1].is_virt_csrow = true; layers 1064 drivers/edac/i5100_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, layers 1190 drivers/edac/i5400_edac.c for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; layers 1192 drivers/edac/i5400_edac.c for (slot = 0; slot < mci->layers[2].size; slot++) { layers 1199 drivers/edac/i5400_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, layers 1266 drivers/edac/i5400_edac.c struct edac_mc_layer layers[3]; layers 1284 drivers/edac/i5400_edac.c layers[0].type = EDAC_MC_LAYER_BRANCH; layers 1285 drivers/edac/i5400_edac.c layers[0].size = MAX_BRANCHES; layers 1286 drivers/edac/i5400_edac.c layers[0].is_virt_csrow = false; layers 1287 drivers/edac/i5400_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 1288 drivers/edac/i5400_edac.c layers[1].size = CHANNELS_PER_BRANCH; layers 1289 drivers/edac/i5400_edac.c layers[1].is_virt_csrow = false; layers 1290 drivers/edac/i5400_edac.c layers[2].type = EDAC_MC_LAYER_SLOT; layers 1291 drivers/edac/i5400_edac.c layers[2].size = DIMMS_PER_CHANNEL; layers 1292 drivers/edac/i5400_edac.c layers[2].is_virt_csrow = true; layers 1293 drivers/edac/i5400_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 797 drivers/edac/i7300_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 1025 drivers/edac/i7300_edac.c struct edac_mc_layer layers[3]; layers 1043 drivers/edac/i7300_edac.c layers[0].type = EDAC_MC_LAYER_BRANCH; layers 1044 drivers/edac/i7300_edac.c layers[0].size = MAX_BRANCHES; layers 1045 drivers/edac/i7300_edac.c layers[0].is_virt_csrow = false; layers 1046 drivers/edac/i7300_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 1047 drivers/edac/i7300_edac.c layers[1].size = MAX_CH_PER_BRANCH; layers 1048 drivers/edac/i7300_edac.c layers[1].is_virt_csrow = true; layers 1049 drivers/edac/i7300_edac.c layers[2].type = EDAC_MC_LAYER_SLOT; layers 1050 drivers/edac/i7300_edac.c layers[2].size = MAX_SLOTS; layers 1051 drivers/edac/i7300_edac.c layers[2].is_virt_csrow = true; layers 1052 drivers/edac/i7300_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 588 drivers/edac/i7core_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, layers 2134 drivers/edac/i7core_edac.c struct edac_mc_layer layers[2]; layers 2138 drivers/edac/i7core_edac.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 2139 drivers/edac/i7core_edac.c layers[0].size = NUM_CHANS; layers 2140 drivers/edac/i7core_edac.c layers[0].is_virt_csrow = false; layers 2141 drivers/edac/i7core_edac.c layers[1].type = EDAC_MC_LAYER_SLOT; layers 2142 drivers/edac/i7core_edac.c layers[1].size = MAX_DIMMS; layers 2143 drivers/edac/i7core_edac.c layers[1].is_virt_csrow = true; layers 2144 drivers/edac/i7core_edac.c mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers, layers 235 drivers/edac/i82443bxgx_edac.c struct edac_mc_layer layers[2]; layers 249 drivers/edac/i82443bxgx_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 250 drivers/edac/i82443bxgx_edac.c layers[0].size = I82443BXGX_NR_CSROWS; layers 251 drivers/edac/i82443bxgx_edac.c layers[0].is_virt_csrow = true; layers 252 drivers/edac/i82443bxgx_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 253 drivers/edac/i82443bxgx_edac.c layers[1].size = I82443BXGX_NR_CHANS; layers 254 drivers/edac/i82443bxgx_edac.c layers[1].is_virt_csrow = false; layers 255 drivers/edac/i82443bxgx_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 188 drivers/edac/i82860_edac.c struct edac_mc_layer layers[2]; layers 201 drivers/edac/i82860_edac.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 202 drivers/edac/i82860_edac.c layers[0].size = 2; layers 203 drivers/edac/i82860_edac.c layers[0].is_virt_csrow = true; layers 204 drivers/edac/i82860_edac.c layers[1].type = EDAC_MC_LAYER_SLOT; layers 205 drivers/edac/i82860_edac.c layers[1].size = 8; layers 206 drivers/edac/i82860_edac.c layers[1].is_virt_csrow = true; layers 207 drivers/edac/i82860_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 392 drivers/edac/i82875p_edac.c struct edac_mc_layer layers[2]; layers 407 drivers/edac/i82875p_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 408 drivers/edac/i82875p_edac.c layers[0].size = I82875P_NR_CSROWS(nr_chans); layers 409 drivers/edac/i82875p_edac.c layers[0].is_virt_csrow = true; layers 410 drivers/edac/i82875p_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 411 drivers/edac/i82875p_edac.c layers[1].size = nr_chans; layers 412 drivers/edac/i82875p_edac.c layers[1].is_virt_csrow = false; layers 413 drivers/edac/i82875p_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 468 drivers/edac/i82975x_edac.c struct edac_mc_layer layers[2]; layers 541 drivers/edac/i82975x_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 542 drivers/edac/i82975x_edac.c layers[0].size = I82975X_NR_DIMMS; layers 543 drivers/edac/i82975x_edac.c layers[0].is_virt_csrow = true; layers 544 drivers/edac/i82975x_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 545 drivers/edac/i82975x_edac.c layers[1].size = I82975X_NR_CSROWS(chans); layers 546 drivers/edac/i82975x_edac.c layers[1].is_virt_csrow = false; layers 547 drivers/edac/i82975x_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 399 drivers/edac/ie31200_edac.c struct edac_mc_layer layers[2]; layers 419 drivers/edac/ie31200_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 420 drivers/edac/ie31200_edac.c layers[0].size = IE31200_DIMMS; layers 421 drivers/edac/ie31200_edac.c layers[0].is_virt_csrow = true; layers 422 drivers/edac/ie31200_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 423 drivers/edac/ie31200_edac.c layers[1].size = nr_channels; layers 424 drivers/edac/ie31200_edac.c layers[1].is_virt_csrow = false; layers 425 drivers/edac/ie31200_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, layers 493 drivers/edac/ie31200_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 506 drivers/edac/ie31200_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 699 drivers/edac/mv64x60_edac.c struct edac_mc_layer layers[2]; layers 708 drivers/edac/mv64x60_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 709 drivers/edac/mv64x60_edac.c layers[0].size = 1; layers 710 drivers/edac/mv64x60_edac.c layers[0].is_virt_csrow = true; layers 711 drivers/edac/mv64x60_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 712 drivers/edac/mv64x60_edac.c layers[1].size = 1; layers 713 drivers/edac/mv64x60_edac.c layers[1].is_virt_csrow = false; layers 714 drivers/edac/mv64x60_edac.c mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, layers 228 drivers/edac/octeon_edac-lmc.c struct edac_mc_layer layers[1]; layers 233 drivers/edac/octeon_edac-lmc.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 234 drivers/edac/octeon_edac-lmc.c layers[0].size = 1; layers 235 drivers/edac/octeon_edac-lmc.c layers[0].is_virt_csrow = false; layers 246 drivers/edac/octeon_edac-lmc.c mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); layers 278 drivers/edac/octeon_edac-lmc.c mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); layers 183 drivers/edac/pasemi_edac.c struct edac_mc_layer layers[2]; layers 200 drivers/edac/pasemi_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 201 drivers/edac/pasemi_edac.c layers[0].size = PASEMI_EDAC_NR_CSROWS; layers 202 drivers/edac/pasemi_edac.c layers[0].is_virt_csrow = true; layers 203 drivers/edac/pasemi_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 204 drivers/edac/pasemi_edac.c layers[1].size = PASEMI_EDAC_NR_CHANS; layers 205 drivers/edac/pasemi_edac.c layers[1].is_virt_csrow = false; layers 206 drivers/edac/pasemi_edac.c mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, layers 1234 drivers/edac/pnd2_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, 0, 0); layers 1314 drivers/edac/pnd2_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0); layers 1334 drivers/edac/pnd2_edac.c struct edac_mc_layer layers[2]; layers 1344 drivers/edac/pnd2_edac.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 1345 drivers/edac/pnd2_edac.c layers[0].size = ops->channels; layers 1346 drivers/edac/pnd2_edac.c layers[0].is_virt_csrow = false; layers 1347 drivers/edac/pnd2_edac.c layers[1].type = EDAC_MC_LAYER_SLOT; layers 1348 drivers/edac/pnd2_edac.c layers[1].size = ops->dimms_per_channel; layers 1349 drivers/edac/pnd2_edac.c layers[1].is_virt_csrow = true; layers 1350 drivers/edac/pnd2_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); layers 1229 drivers/edac/ppc4xx_edac.c struct edac_mc_layer layers[2]; layers 1275 drivers/edac/ppc4xx_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 1276 drivers/edac/ppc4xx_edac.c layers[0].size = ppc4xx_edac_nr_csrows; layers 1277 drivers/edac/ppc4xx_edac.c layers[0].is_virt_csrow = true; layers 1278 drivers/edac/ppc4xx_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 1279 drivers/edac/ppc4xx_edac.c layers[1].size = ppc4xx_edac_nr_chans; layers 1280 drivers/edac/ppc4xx_edac.c layers[1].is_virt_csrow = false; layers 1281 drivers/edac/ppc4xx_edac.c mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers, layers 272 drivers/edac/r82600_edac.c struct edac_mc_layer layers[2]; layers 286 drivers/edac/r82600_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 287 drivers/edac/r82600_edac.c layers[0].size = R82600_NR_CSROWS; layers 288 drivers/edac/r82600_edac.c layers[0].is_virt_csrow = true; layers 289 drivers/edac/r82600_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 290 drivers/edac/r82600_edac.c layers[1].size = R82600_NR_CHANS; layers 291 drivers/edac/r82600_edac.c layers[1].is_virt_csrow = false; layers 292 drivers/edac/r82600_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 1623 drivers/edac/sb_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0); layers 3229 drivers/edac/sb_edac.c struct edac_mc_layer layers[2]; layers 3235 drivers/edac/sb_edac.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 3236 drivers/edac/sb_edac.c layers[0].size = type == KNIGHTS_LANDING ? layers 3238 drivers/edac/sb_edac.c layers[0].is_virt_csrow = false; layers 3239 drivers/edac/sb_edac.c layers[1].type = EDAC_MC_LAYER_SLOT; layers 3240 drivers/edac/sb_edac.c layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS; layers 3241 drivers/edac/sb_edac.c layers[1].is_virt_csrow = true; layers 3242 drivers/edac/sb_edac.c mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, layers 176 drivers/edac/skx_base.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, layers 376 drivers/edac/skx_common.c struct edac_mc_layer layers[2]; layers 381 drivers/edac/skx_common.c layers[0].type = EDAC_MC_LAYER_CHANNEL; layers 382 drivers/edac/skx_common.c layers[0].size = NUM_CHANNELS; layers 383 drivers/edac/skx_common.c layers[0].is_virt_csrow = false; layers 384 drivers/edac/skx_common.c layers[1].type = EDAC_MC_LAYER_SLOT; layers 385 drivers/edac/skx_common.c layers[1].size = NUM_DIMMS; layers 386 drivers/edac/skx_common.c layers[1].is_virt_csrow = true; layers 387 drivers/edac/skx_common.c mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, layers 1290 drivers/edac/synopsys_edac.c struct edac_mc_layer layers[2]; layers 1311 drivers/edac/synopsys_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 1312 drivers/edac/synopsys_edac.c layers[0].size = SYNPS_EDAC_NR_CSROWS; layers 1313 drivers/edac/synopsys_edac.c layers[0].is_virt_csrow = true; layers 1314 drivers/edac/synopsys_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 1315 drivers/edac/synopsys_edac.c layers[1].size = SYNPS_EDAC_NR_CHANS; layers 1316 drivers/edac/synopsys_edac.c layers[1].is_virt_csrow = false; layers 1318 drivers/edac/synopsys_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, layers 138 drivers/edac/ti_edac.c dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); layers 236 drivers/edac/ti_edac.c struct edac_mc_layer layers[1]; layers 253 drivers/edac/ti_edac.c layers[0].type = EDAC_MC_LAYER_ALL_MEM; layers 254 drivers/edac/ti_edac.c layers[0].size = 1; layers 261 drivers/edac/ti_edac.c mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac)); layers 323 drivers/edac/x38_edac.c struct edac_mc_layer layers[2]; layers 339 drivers/edac/x38_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 340 drivers/edac/x38_edac.c layers[0].size = X38_RANKS; layers 341 drivers/edac/x38_edac.c layers[0].is_virt_csrow = true; layers 342 drivers/edac/x38_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 343 drivers/edac/x38_edac.c layers[1].size = x38_channel_num; layers 344 drivers/edac/x38_edac.c layers[1].is_virt_csrow = false; layers 345 drivers/edac/x38_edac.c mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); layers 345 drivers/edac/xgene_edac.c struct edac_mc_layer layers[2]; layers 380 drivers/edac/xgene_edac.c layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers 381 drivers/edac/xgene_edac.c layers[0].size = 4; layers 382 drivers/edac/xgene_edac.c layers[0].is_virt_csrow = true; layers 383 drivers/edac/xgene_edac.c layers[1].type = EDAC_MC_LAYER_CHANNEL; layers 384 drivers/edac/xgene_edac.c layers[1].size = 2; layers 385 drivers/edac/xgene_edac.c layers[1].is_virt_csrow = false; layers 386 drivers/edac/xgene_edac.c mci = edac_mc_alloc(tmp_ctx.mcu_id, ARRAY_SIZE(layers), layers, layers 81 drivers/gpu/drm/arm/display/komeda/komeda_dev.c config_id.max_line_sz = pipe->layers[0]->hsize_in.end; layers 87 drivers/gpu/drm/arm/display/komeda/komeda_dev.c if (pipe->layers[i]->layer_type == KOMEDA_FMT_RICH_LAYER) layers 77 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c pos = to_cpos(pipe->layers[id - KOMEDA_COMPONENT_LAYER0]); layers 294 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c if (left->layer_type == pipe->layers[i]->layer_type) layers 295 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c return pipe->layers[i]; layers 311 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c layer = pipe->layers[i]; layers 395 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS]; layers 330 drivers/gpu/drm/arm/display/komeda/komeda_plane.c err = komeda_plane_add(kms, pipe->layers[j]); layers 380 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c err = komeda_layer_obj_add(kms, pipe->layers[j]); layers 936 drivers/gpu/drm/arm/malidp_hw.c .layers = malidp500_layers, layers 988 drivers/gpu/drm/arm/malidp_hw.c .layers = malidp550_layers, layers 1036 drivers/gpu/drm/arm/malidp_hw.c .layers = malidp650_layers, layers 117 drivers/gpu/drm/arm/malidp_hw.h const struct malidp_layer *layers; layers 966 drivers/gpu/drm/arm/malidp_planes.c u8 id = map->layers[i].id; layers 997 drivers/gpu/drm/arm/malidp_planes.c plane->layer = &map->layers[i]; layers 495 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c if (!dc->layers[i]) layers 498 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c switch (dc->layers[i]->desc->type) { layers 500 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c primary = atmel_hlcdc_layer_to_plane(dc->layers[i]); layers 504 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]); layers 523 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c if (dc->layers[i] && layers 524 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) { layers 525 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]); layers 60 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c .layers = atmel_hlcdc_at91sam9n12_layers, layers 153 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c .layers = atmel_hlcdc_at91sam9x5_layers, layers 271 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c .layers = atmel_hlcdc_sama5d3_layers, layers 366 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c .layers = atmel_hlcdc_sama5d4_layers, layers 462 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c .layers = atmel_hlcdc_sam9x60_layers, layers 554 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c atmel_hlcdc_layer_irq(dc->layers[i]); layers 817 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c if (dc->layers[i]) layers 320 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h const struct atmel_hlcdc_layer_desc *layers; layers 343 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; layers 987 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c dc->layers[desc->id] = &plane->layer; layers 995 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers; layers 201 drivers/media/dvb-frontends/tc90522.c int layers; layers 209 drivers/media/dvb-frontends/tc90522.c layers = 0; layers 236 drivers/media/dvb-frontends/tc90522.c layers = (v > 0) ? 2 : 1; layers 284 drivers/media/dvb-frontends/tc90522.c stats->len = layers; layers 287 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) layers 290 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) { layers 298 drivers/media/dvb-frontends/tc90522.c stats->len = layers; layers 300 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) layers 303 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) { layers 336 drivers/media/dvb-frontends/tc90522.c int layers; layers 352 drivers/media/dvb-frontends/tc90522.c layers = 0; layers 364 drivers/media/dvb-frontends/tc90522.c layers++; layers 377 drivers/media/dvb-frontends/tc90522.c layers++; layers 389 drivers/media/dvb-frontends/tc90522.c layers++; layers 444 drivers/media/dvb-frontends/tc90522.c stats->len = layers; layers 447 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) layers 450 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) { layers 458 drivers/media/dvb-frontends/tc90522.c stats->len = layers; layers 460 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) layers 463 drivers/media/dvb-frontends/tc90522.c for (i = 0; i < layers; i++) { layers 1037 drivers/media/platform/qcom/venus/hfi_cmds.c hierp->layers = in->layers; layers 1094 drivers/media/platform/qcom/venus/hfi_helper.h u32 layers; layers 359 drivers/parisc/pdc_stable.c for (i = 0; i < 6 && devpath->layers[i]; i++) layers 360 drivers/parisc/pdc_stable.c out += sprintf(out, "%u ", devpath->layers[i]); layers 382 drivers/parisc/pdc_stable.c unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ layers 395 drivers/parisc/pdc_stable.c memset(&layers, 0, sizeof(layers)); layers 400 drivers/parisc/pdc_stable.c layers[0] = simple_strtoul(in, NULL, 10); layers 401 drivers/parisc/pdc_stable.c DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); layers 407 drivers/parisc/pdc_stable.c layers[i] = simple_strtoul(temp, NULL, 10); layers 408 drivers/parisc/pdc_stable.c DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); layers 416 drivers/parisc/pdc_stable.c memcpy(&entry->devpath.layers, &layers, sizeof(layers)); layers 392 include/linux/edac.h #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ layers 397 include/linux/edac.h __i = (layer1) + ((layers[1]).size * (layer0)); \ layers 399 include/linux/edac.h __i = (layer2) + ((layers[2]).size * ((layer1) + \ layers 400 include/linux/edac.h ((layers[1]).size * (layer0)))); \ layers 427 include/linux/edac.h #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ layers 429 include/linux/edac.h int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \ layers 612 include/linux/edac.h struct edac_mc_layer *layers;