layer 1796 drivers/cdrom/cdrom.c struct dvd_layer *layer; layer 1819 drivers/cdrom/cdrom.c layer = &s->physical.layer[layer_num]; layer 1825 drivers/cdrom/cdrom.c memset(layer, 0, sizeof(*layer)); layer 1826 drivers/cdrom/cdrom.c layer->book_version = base[0] & 0xf; layer 1827 drivers/cdrom/cdrom.c layer->book_type = base[0] >> 4; layer 1828 drivers/cdrom/cdrom.c layer->min_rate = base[1] & 0xf; layer 1829 drivers/cdrom/cdrom.c layer->disc_size = base[1] >> 4; layer 1830 drivers/cdrom/cdrom.c layer->layer_type = base[2] & 0xf; layer 1831 drivers/cdrom/cdrom.c layer->track_path = (base[2] >> 4) & 1; layer 1832 drivers/cdrom/cdrom.c layer->nlayers = (base[2] >> 5) & 3; layer 1833 drivers/cdrom/cdrom.c layer->track_density = base[3] & 0xf; layer 1834 drivers/cdrom/cdrom.c layer->linear_density = base[3] >> 4; layer 1835 drivers/cdrom/cdrom.c layer->start_sector = base[5] << 16 | base[6] << 8 | base[7]; layer 1836 drivers/cdrom/cdrom.c layer->end_sector = base[9] << 16 | base[10] << 8 | base[11]; layer 1837 drivers/cdrom/cdrom.c layer->end_sector_l0 = base[13] << 16 | base[14] << 8 | base[15]; layer 1838 drivers/cdrom/cdrom.c layer->bca = base[16] >> 7; layer 311 drivers/edac/edac_mc.c struct edac_mc_layer *layer; layer 345 drivers/edac/edac_mc.c layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); layer 371 drivers/edac/edac_mc.c layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); layer 383 drivers/edac/edac_mc.c mci->layers = layer; layer 384 drivers/edac/edac_mc.c memcpy(mci->layers, layers, sizeof(*layer) * n_layers); layer 430 drivers/edac/edac_mc.c off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); layer 665 drivers/edac/thunderx_edac.c struct edac_mc_layer layer; layer 672 drivers/edac/thunderx_edac.c layer.type = EDAC_MC_LAYER_SLOT; layer 673 drivers/edac/thunderx_edac.c layer.size = 2; layer 674 drivers/edac/thunderx_edac.c layer.is_virt_csrow = false; layer 688 drivers/edac/thunderx_edac.c mci = edac_mc_alloc(pci_dev_to_mc_idx(pdev), 1, &layer, layer 345 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct komeda_layer *layer; layer 349 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*layer), layer 360 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c layer = to_layer(c); layer 364 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c layer->layer_type = KOMEDA_FMT_RICH_LAYER; layer 366 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c layer->layer_type = KOMEDA_FMT_SIMPLE_LAYER; layer 368 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&layer->hsize_in, 4, d71->max_line_size); layer 369 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&layer->vsize_in, 4, d71->max_vsize); layer 373 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c layer->supported_rots = DRM_MODE_ROTATE_MASK | DRM_MODE_REFLECT_MASK; layer 547 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c if (kplane->layer->base.pipeline == crtc->master) layer 33 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct komeda_layer *layer; layer 302 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c struct komeda_layer *layer; layer 311 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c layer = pipe->layers[i]; layer 313 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c layer->right = komeda_get_layer_split_right_layer(pipe, layer); layer 512 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h int komeda_build_layer_data_flow(struct komeda_layer *layer, layer 543 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h void komeda_complete_data_flow_cfg(struct komeda_layer *layer, layer 283 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_layer_check_cfg(struct komeda_layer *layer, layer 289 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c if (!komeda_fb_is_layer_supported(kfb, layer->layer_type, dflow->rot)) layer 292 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c if (layer->base.id == KOMEDA_COMPONENT_WB_LAYER) { layer 307 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c if (!in_range(&layer->hsize_in, src_w)) { layer 312 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c if (!in_range(&layer->vsize_in, src_h)) { layer 321 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_layer_validate(struct komeda_layer *layer, layer 332 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c err = komeda_layer_check_cfg(layer, kfb, dflow); layer 336 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&layer->base, layer 365 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c err = komeda_component_validate_private(&layer->base, c_st); layer 370 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &layer->base, 0); layer 787 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c void komeda_complete_data_flow_cfg(struct komeda_layer *layer, layer 791 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_scaler *scaler = layer->base.pipeline->scalers[0]; layer 830 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c int komeda_build_layer_data_flow(struct komeda_layer *layer, layer 836 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = layer->base.pipeline; layer 840 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c layer->base.name, plane->base.id, plane->name, layer 844 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c err = komeda_layer_validate(layer, kplane_st, dflow); layer 23 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_pipeline *pipe = kplane->layer->base.pipeline; layer 59 drivers/gpu/drm/arm/display/komeda/komeda_plane.c komeda_complete_data_flow_cfg(kplane->layer, dflow, fb); layer 78 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_layer *layer = kplane->layer; layer 104 drivers/gpu/drm/arm/display/komeda/komeda_plane.c err = komeda_build_layer_split_data_flow(layer, layer 107 drivers/gpu/drm/arm/display/komeda/komeda_plane.c err = komeda_build_layer_data_flow(layer, layer 150 drivers/gpu/drm/arm/display/komeda/komeda_plane.c state->base.zpos = kplane->layer->base.id; layer 189 drivers/gpu/drm/arm/display/komeda/komeda_plane.c u32 layer_type = kplane->layer->layer_type; layer 249 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_layer *layer) layer 252 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_component *c = &layer->base; layer 263 drivers/gpu/drm/arm/display/komeda/komeda_plane.c kplane->layer = layer; layer 266 drivers/gpu/drm/arm/display/komeda/komeda_plane.c layer->layer_type, &n_formats); layer 283 drivers/gpu/drm/arm/display/komeda/komeda_plane.c layer->supported_rots); layer 309 drivers/gpu/drm/arm/display/komeda/komeda_plane.c err = drm_plane_create_zpos_property(plane, layer->base.id, 0, 8); layer 49 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c struct komeda_layer *layer) layer 57 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c st->base.component = &layer->base; layer 58 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c drm_atomic_private_obj_init(&kms->base, &layer->base.obj, &st->base.obj, layer 275 drivers/gpu/drm/arm/malidp_crtc.c if (!(mp->layer->id & scaling)) layer 322 drivers/gpu/drm/arm/malidp_crtc.c s->plane_src_id = mp->layer->id; layer 403 drivers/gpu/drm/arm/malidp_crtc.c if ((mp->layer->id != DE_VIDEO1) || layer 52 drivers/gpu/drm/arm/malidp_drv.h const struct malidp_layer *layer; layer 1088 drivers/gpu/drm/arm/malidp_hw.c if (((map->pixel_formats[i].layer & layer_id) == layer_id) && layer 43 drivers/gpu/drm/arm/malidp_hw.h u8 layer; /* bitmask of layers supporting it */ layer 200 drivers/gpu/drm/arm/malidp_mw.c if (map->pixel_formats[i].layer & SE_MEMWRITE) layer 299 drivers/gpu/drm/arm/malidp_planes.c mc->scaled_planes_mask &= ~(mp->layer->id); layer 303 drivers/gpu/drm/arm/malidp_planes.c if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) layer 306 drivers/gpu/drm/arm/malidp_planes.c mc->scaled_planes_mask |= mp->layer->id; layer 495 drivers/gpu/drm/arm/malidp_planes.c if (!mp->layer->mmu_ctrl_offset) layer 521 drivers/gpu/drm/arm/malidp_planes.c mp->layer->id, fb->format->format, layer 571 drivers/gpu/drm/arm/malidp_planes.c if (mp->layer->rot == ROTATE_NONE) layer 573 drivers/gpu/drm/arm/malidp_planes.c if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) layer 585 drivers/gpu/drm/arm/malidp_planes.c if (mp->layer->id == DE_SMART && fb->modifier) { layer 621 drivers/gpu/drm/arm/malidp_planes.c if (!mp->layer->stride_offset) layer 637 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + layer 638 drivers/gpu/drm/arm/malidp_planes.c mp->layer->stride_offset + i * 4); layer 691 drivers/gpu/drm/arm/malidp_planes.c plane->layer->base + plane->layer->yuv2rgb_offset + layer 702 drivers/gpu/drm/arm/malidp_planes.c if (!mp->layer->mmu_ctrl_offset) layer 711 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + mp->layer->mmu_ctrl_offset); layer 723 drivers/gpu/drm/arm/malidp_planes.c ptr = mp->layer->ptr + (plane_index << 4); layer 758 drivers/gpu/drm/arm/malidp_planes.c if (!mp->layer->afbc_decoder_offset) layer 762 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset); layer 775 drivers/gpu/drm/arm/malidp_planes.c mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H); layer 780 drivers/gpu/drm/arm/malidp_planes.c mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V); layer 788 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); layer 821 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base); layer 823 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->base); layer 839 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_SIZE); layer 842 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_COMP_SIZE); layer 846 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_OFFSET); layer 848 drivers/gpu/drm/arm/malidp_planes.c if (mp->layer->id == DE_SMART) { layer 854 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP550_LS_ENABLE); layer 857 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP550_LS_R1_IN_SIZE); layer 863 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); layer 898 drivers/gpu/drm/arm/malidp_planes.c m->scaler_config.plane_src_id == mp->layer->id) layer 906 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_CONTROL); layer 916 drivers/gpu/drm/arm/malidp_planes.c mp->layer->base + MALIDP_LAYER_CONTROL); layer 976 drivers/gpu/drm/arm/malidp_planes.c if ((map->pixel_formats[j].layer & id) == id) layer 997 drivers/gpu/drm/arm/malidp_planes.c plane->layer = &map->layers[i]; layer 1009 drivers/gpu/drm/arm/malidp_planes.c plane->layer->base + MALIDP_LAYER_COMPOSE); layer 524 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer) layer 526 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c if (!layer) layer 529 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER || layer 530 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER || layer 531 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER) layer 532 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer)); layer 276 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h struct atmel_hlcdc_layer layer; layer 286 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) layer 288 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h return container_of(layer, struct atmel_hlcdc_plane, layer); layer 358 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer, layer 361 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_write(layer->regmap, layer->desc->regs_offset + reg, val); layer 364 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer, layer 369 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val); layer 374 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer, layer 377 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h atmel_hlcdc_layer_write_reg(layer, layer 378 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h layer->desc->cfgs_offset + layer 382 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer, layer 385 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h return atmel_hlcdc_layer_read_reg(layer, layer 386 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h layer->desc->cfgs_offset + layer 390 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer, layer 393 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_write(layer->regmap, layer 394 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h layer->desc->clut_offset + c * sizeof(u32), layer 398 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer, layer 402 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h layer->desc = desc; layer 403 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h layer->regmap = regmap; layer 279 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, layer 286 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 293 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 325 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, layer 335 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 338 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, layer 343 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 349 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.pos, layer 361 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 371 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, layer 390 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config, layer 410 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 434 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_clut(&plane->layer, idx, val); layer 441 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 446 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); layer 453 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, layer 458 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, layer 461 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, layer 464 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, layer 470 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 475 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 527 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c layout = &primary->layer.desc->layout; layer 581 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c layout = &plane->layer.desc->layout; layer 585 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_pos, layer 589 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_size, layer 600 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 721 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, layer 725 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR, layer 731 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); layer 758 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, layer 764 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); layer 765 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, layer 773 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 802 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 805 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 808 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_write_cfg(&plane->layer, layer 818 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; layer 821 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); layer 962 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap); layer 987 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c dc->layers[desc->id] = &plane->layer; layer 117 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) layer 80 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, bool enable) layer 85 drivers/gpu/drm/sun4i/sun4i_backend.c layer); layer 88 drivers/gpu/drm/sun4i/sun4i_backend.c val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); layer 93 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); layer 168 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, struct drm_plane *plane) layer 172 drivers/gpu/drm/sun4i/sun4i_backend.c DRM_DEBUG_DRIVER("Updating layer %d\n", layer); layer 185 drivers/gpu/drm/sun4i/sun4i_backend.c regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer), layer 192 drivers/gpu/drm/sun4i/sun4i_backend.c regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer), layer 200 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, struct drm_plane *plane) layer 218 drivers/gpu/drm/sun4i/sun4i_backend.c regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), layer 257 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, struct drm_plane *plane) layer 266 drivers/gpu/drm/sun4i/sun4i_backend.c regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), layer 284 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG0(layer), layer 290 drivers/gpu/drm/sun4i/sun4i_backend.c return sun4i_backend_update_yuv_format(backend, layer, plane); layer 299 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG1(layer), layer 306 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, uint32_t fmt) layer 318 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG0(layer), layer 323 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG1(layer), layer 345 drivers/gpu/drm/sun4i/sun4i_backend.c int layer, struct drm_plane *plane) layer 355 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_LAYLINEWIDTH_REG(layer), layer 369 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_LAYFB_L32ADD_REG(layer), layer 376 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer), layer 377 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr)); layer 382 drivers/gpu/drm/sun4i/sun4i_backend.c int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, layer 391 drivers/gpu/drm/sun4i/sun4i_backend.c layer, priority, pipe); layer 392 drivers/gpu/drm/sun4i/sun4i_backend.c regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), layer 402 drivers/gpu/drm/sun4i/sun4i_backend.c int layer) layer 405 drivers/gpu/drm/sun4i/sun4i_backend.c SUN4I_BACKEND_ATTCTL_REG0(layer), layer 426 drivers/gpu/drm/sun4i/sun4i_backend.c struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); layer 427 drivers/gpu/drm/sun4i/sun4i_backend.c struct sun4i_backend *backend = layer->backend; layer 196 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, bool enable); layer 199 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, struct drm_plane *plane); layer 201 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, struct drm_plane *plane); layer 203 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, struct drm_plane *plane); layer 205 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, uint32_t in_fmt); layer 207 drivers/gpu/drm/sun4i/sun4i_backend.h int layer, struct drm_plane *plane); layer 209 drivers/gpu/drm/sun4i/sun4i_backend.h int layer); layer 20 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_layer *layer = plane_to_sun4i_layer(plane); layer 35 drivers/gpu/drm/sun4i/sun4i_layer.c plane->state->zpos = layer->id; layer 69 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_layer *layer = plane_to_sun4i_layer(plane); layer 70 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_backend *backend = layer->backend; layer 72 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_layer_enable(backend, layer->id, false); layer 87 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_layer *layer = plane_to_sun4i_layer(plane); layer 88 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_backend *backend = layer->backend; layer 91 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_cleanup_layer(backend, layer->id); layer 99 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_update_layer_frontend(backend, layer->id, layer 103 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_update_layer_formats(backend, layer->id, plane); layer 104 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_update_layer_buffer(backend, layer->id, plane); layer 107 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_update_layer_coord(backend, layer->id, plane); layer 108 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_update_layer_zpos(backend, layer->id, plane); layer 109 drivers/gpu/drm/sun4i/sun4i_layer.c sun4i_backend_layer_enable(backend, layer->id, true); layer 115 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_layer *layer = plane_to_sun4i_layer(plane); layer 117 drivers/gpu/drm/sun4i/sun4i_layer.c if (IS_ERR_OR_NULL(layer->backend->frontend)) layer 196 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_layer *layer; layer 199 drivers/gpu/drm/sun4i/sun4i_layer.c layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); layer 200 drivers/gpu/drm/sun4i/sun4i_layer.c if (!layer) layer 203 drivers/gpu/drm/sun4i/sun4i_layer.c layer->backend = backend; layer 212 drivers/gpu/drm/sun4i/sun4i_layer.c ret = drm_universal_plane_init(drm, &layer->plane, 0, layer 221 drivers/gpu/drm/sun4i/sun4i_layer.c drm_plane_helper_add(&layer->plane, layer 224 drivers/gpu/drm/sun4i/sun4i_layer.c drm_plane_create_alpha_property(&layer->plane); layer 225 drivers/gpu/drm/sun4i/sun4i_layer.c drm_plane_create_zpos_property(&layer->plane, 0, 0, layer 228 drivers/gpu/drm/sun4i/sun4i_layer.c return layer; layer 246 drivers/gpu/drm/sun4i/sun4i_layer.c struct sun4i_layer *layer; layer 248 drivers/gpu/drm/sun4i/sun4i_layer.c layer = sun4i_layer_init_one(drm, backend, type); layer 249 drivers/gpu/drm/sun4i/sun4i_layer.c if (IS_ERR(layer)) { layer 252 drivers/gpu/drm/sun4i/sun4i_layer.c return ERR_CAST(layer); layer 255 drivers/gpu/drm/sun4i/sun4i_layer.c layer->id = i; layer 256 drivers/gpu/drm/sun4i/sun4i_layer.c planes[i] = &layer->plane; layer 177 drivers/gpu/drm/sun4i/sun8i_csc.c static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, layer 197 drivers/gpu/drm/sun4i/sun8i_csc.c base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0); layer 213 drivers/gpu/drm/sun4i/sun8i_csc.c static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) layer 217 drivers/gpu/drm/sun4i/sun8i_csc.c mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); layer 228 drivers/gpu/drm/sun4i/sun8i_csc.c void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, layer 236 drivers/gpu/drm/sun4i/sun8i_csc.c sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, layer 241 drivers/gpu/drm/sun4i/sun8i_csc.c base = ccsc_base[mixer->cfg->ccsc][layer]; layer 247 drivers/gpu/drm/sun4i/sun8i_csc.c void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) layer 252 drivers/gpu/drm/sun4i/sun8i_csc.c sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable); layer 256 drivers/gpu/drm/sun4i/sun8i_csc.c base = ccsc_base[mixer->cfg->ccsc][layer]; layer 30 drivers/gpu/drm/sun4i/sun8i_csc.h void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, layer 34 drivers/gpu/drm/sun4i/sun8i_csc.h void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable); layer 362 drivers/gpu/drm/sun4i/sun8i_mixer.c struct sun8i_vi_layer *layer; layer 364 drivers/gpu/drm/sun4i/sun8i_mixer.c layer = sun8i_vi_layer_init_one(drm, mixer, i); layer 365 drivers/gpu/drm/sun4i/sun8i_mixer.c if (IS_ERR(layer)) { layer 368 drivers/gpu/drm/sun4i/sun8i_mixer.c return ERR_CAST(layer); layer 371 drivers/gpu/drm/sun4i/sun8i_mixer.c planes[i] = &layer->plane; layer 375 drivers/gpu/drm/sun4i/sun8i_mixer.c struct sun8i_ui_layer *layer; layer 377 drivers/gpu/drm/sun4i/sun8i_mixer.c layer = sun8i_ui_layer_init_one(drm, mixer, i); layer 378 drivers/gpu/drm/sun4i/sun8i_mixer.c if (IS_ERR(layer)) { layer 381 drivers/gpu/drm/sun4i/sun8i_mixer.c return ERR_CAST(layer); layer 384 drivers/gpu/drm/sun4i/sun8i_mixer.c planes[mixer->cfg->vi_num + i] = &layer->plane; layer 54 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \ layer 55 drivers/gpu/drm/sun4i/sun8i_mixer.h ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y)) layer 56 drivers/gpu/drm/sun4i/sun8i_mixer.h #define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \ layer 57 drivers/gpu/drm/sun4i/sun8i_mixer.h ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c) layer 239 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); layer 254 drivers/gpu/drm/sun4i/sun8i_ui_layer.c if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { layer 267 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); layer 269 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_mixer *mixer = layer->mixer; layer 271 drivers/gpu/drm/sun4i/sun8i_ui_layer.c sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, layer 278 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); layer 281 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_mixer *mixer = layer->mixer; layer 284 drivers/gpu/drm/sun4i/sun8i_ui_layer.c sun8i_ui_layer_enable(mixer, layer->channel, layer 285 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->overlay, false, 0, old_zpos); layer 289 drivers/gpu/drm/sun4i/sun8i_ui_layer.c sun8i_ui_layer_update_coord(mixer, layer->channel, layer 290 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->overlay, plane, zpos); layer 291 drivers/gpu/drm/sun4i/sun8i_ui_layer.c sun8i_ui_layer_update_formats(mixer, layer->channel, layer 292 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->overlay, plane); layer 293 drivers/gpu/drm/sun4i/sun8i_ui_layer.c sun8i_ui_layer_update_buffer(mixer, layer->channel, layer 294 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->overlay, plane); layer 295 drivers/gpu/drm/sun4i/sun8i_ui_layer.c sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, layer 344 drivers/gpu/drm/sun4i/sun8i_ui_layer.c struct sun8i_ui_layer *layer; layer 348 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); layer 349 drivers/gpu/drm/sun4i/sun8i_ui_layer.c if (!layer) layer 356 drivers/gpu/drm/sun4i/sun8i_ui_layer.c ret = drm_universal_plane_init(drm, &layer->plane, 0, layer 368 drivers/gpu/drm/sun4i/sun8i_ui_layer.c ret = drm_plane_create_zpos_property(&layer->plane, channel, layer 375 drivers/gpu/drm/sun4i/sun8i_ui_layer.c drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs); layer 376 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->mixer = mixer; layer 377 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->channel = channel; layer 378 drivers/gpu/drm/sun4i/sun8i_ui_layer.c layer->overlay = 0; layer 380 drivers/gpu/drm/sun4i/sun8i_ui_layer.c return layer; layer 17 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ layer 18 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x0) layer 19 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ layer 20 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x4) layer 21 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ layer 22 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x8) layer 23 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ layer 24 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0xc) layer 25 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ layer 26 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x10) layer 27 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ layer 28 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x14) layer 29 drivers/gpu/drm/sun4i/sun8i_ui_layer.h #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ layer 30 drivers/gpu/drm/sun4i/sun8i_ui_layer.h ((base) + 0x20 * (layer) + 0x18) layer 130 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) layer 134 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c if (WARN_ON(layer < mixer->cfg->vi_num)) layer 137 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c base = sun8i_ui_scaler_base(mixer, layer); layer 148 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer, layer 156 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c if (WARN_ON(layer < mixer->cfg->vi_num)) layer 159 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c base = sun8i_ui_scaler_base(mixer, layer); layer 38 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable); layer 39 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer, layer 324 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); layer 339 drivers/gpu/drm/sun4i/sun8i_vi_layer.c if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { layer 352 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); layer 354 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_mixer *mixer = layer->mixer; layer 356 drivers/gpu/drm/sun4i/sun8i_vi_layer.c sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0, layer 363 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); layer 366 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_mixer *mixer = layer->mixer; layer 369 drivers/gpu/drm/sun4i/sun8i_vi_layer.c sun8i_vi_layer_enable(mixer, layer->channel, layer 370 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->overlay, false, 0, old_zpos); layer 374 drivers/gpu/drm/sun4i/sun8i_vi_layer.c sun8i_vi_layer_update_coord(mixer, layer->channel, layer 375 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->overlay, plane, zpos); layer 376 drivers/gpu/drm/sun4i/sun8i_vi_layer.c sun8i_vi_layer_update_formats(mixer, layer->channel, layer 377 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->overlay, plane); layer 378 drivers/gpu/drm/sun4i/sun8i_vi_layer.c sun8i_vi_layer_update_buffer(mixer, layer->channel, layer 379 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->overlay, plane); layer 380 drivers/gpu/drm/sun4i/sun8i_vi_layer.c sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, layer 489 drivers/gpu/drm/sun4i/sun8i_vi_layer.c struct sun8i_vi_layer *layer; layer 493 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); layer 494 drivers/gpu/drm/sun4i/sun8i_vi_layer.c if (!layer) layer 506 drivers/gpu/drm/sun4i/sun8i_vi_layer.c ret = drm_universal_plane_init(drm, &layer->plane, 0, layer 517 drivers/gpu/drm/sun4i/sun8i_vi_layer.c ret = drm_plane_create_zpos_property(&layer->plane, index, layer 530 drivers/gpu/drm/sun4i/sun8i_vi_layer.c ret = drm_plane_create_color_properties(&layer->plane, layer 540 drivers/gpu/drm/sun4i/sun8i_vi_layer.c drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs); layer 541 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->mixer = mixer; layer 542 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->channel = index; layer 543 drivers/gpu/drm/sun4i/sun8i_vi_layer.c layer->overlay = 0; layer 545 drivers/gpu/drm/sun4i/sun8i_vi_layer.c return layer; layer 11 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ layer 12 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x0) layer 13 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ layer 14 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x4) layer 15 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ layer 16 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x8) layer 17 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ layer 18 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0xc + 4 * (plane)) layer 19 drivers/gpu/drm/sun4i/sun8i_vi_layer.h #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ layer 20 drivers/gpu/drm/sun4i/sun8i_vi_layer.h ((base) + 0x30 * (layer) + 0x18 + 4 * (plane)) layer 910 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) layer 914 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c base = sun8i_vi_scaler_base(mixer, layer); layer 926 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, layer 935 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c base = sun8i_vi_scaler_base(mixer, layer); layer 72 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable); layer 73 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, layer 103 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; layer 105 drivers/gpu/drm/zte/zx_plane.c zx_writel_mask(layer + VL_CTRL0, VL_UPDATE, VL_UPDATE); layer 190 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; layer 216 drivers/gpu/drm/zte/zx_plane.c paddr_reg = layer + VL_Y; layer 227 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); layer 230 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y)); layer 233 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_POS_END, layer 237 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_STRIDE, LUMA_STRIDE(fb->pitches[0]) | layer 243 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + VL_CTRL1, fmt); layer 246 drivers/gpu/drm/zte/zx_plane.c zx_writel_mask(layer + VL_CTRL2, VL_SCALER_BYPASS_MODE, layer 328 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; layer 330 drivers/gpu/drm/zte/zx_plane.c zx_writel_mask(layer + GL_CTRL0, GL_UPDATE, GL_UPDATE); layer 355 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; layer 387 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_ADDR, paddr); layer 390 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); layer 393 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y)); layer 396 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_POS_END, layer 400 drivers/gpu/drm/zte/zx_plane.c zx_writel(layer + GL_STRIDE, stride & 0xffff); layer 405 drivers/gpu/drm/zte/zx_plane.c zx_writel_mask(layer + GL_CTRL1, GL_DATA_FMT_MASK, layer 409 drivers/gpu/drm/zte/zx_plane.c zx_writel_mask(layer + GL_CTRL2, GL_GLOBAL_ALPHA_MASK, layer 422 drivers/gpu/drm/zte/zx_plane.c zx_writel_mask(layer + GL_CTRL3, GL_SCALER_BYPASS_MODE, layer 13 drivers/gpu/drm/zte/zx_plane.h void __iomem *layer; layer 553 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + MAIN_GL_OFFSET; layer 564 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + AUX_GL_OFFSET; layer 658 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + OSD_VL_OFFSET(i); layer 196 drivers/infiniband/sw/siw/iwarp.h __be32 layer : 4; layer 210 drivers/infiniband/sw/siw/iwarp.h __be32 layer : 4; layer 231 drivers/infiniband/sw/siw/iwarp.h return term->layer; layer 235 drivers/infiniband/sw/siw/iwarp.h u8 layer) layer 237 drivers/infiniband/sw/siw/iwarp.h term->layer = layer & 0xf; layer 477 drivers/infiniband/sw/siw/siw.h u8 layer : 4, etype : 4; layer 533 drivers/infiniband/sw/siw/siw.h void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer, layer 363 drivers/infiniband/sw/siw/siw_qp.c void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer, u8 etype, layer 368 drivers/infiniband/sw/siw/siw_qp.c qp->term_info.layer = layer; layer 375 drivers/infiniband/sw/siw/siw_qp.c layer, etype, ecode, in_tx ? "yes" : "no"); layer 428 drivers/infiniband/sw/siw/siw_qp.c if ((qp->term_info.layer == TERM_ERROR_LAYER_DDP) || layer 429 drivers/infiniband/sw/siw/siw_qp.c ((qp->term_info.layer == TERM_ERROR_LAYER_RDMAP) && layer 440 drivers/infiniband/sw/siw/siw_qp.c __rdmap_term_set_layer(term, qp->term_info.layer); layer 444 drivers/infiniband/sw/siw/siw_qp.c switch (qp->term_info.layer) { layer 268 drivers/iommu/mtk_iommu.c bool layer, write; layer 281 drivers/iommu/mtk_iommu.c layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; layer 294 drivers/iommu/mtk_iommu.c layer, write ? "write" : "read"); layer 234 drivers/isdn/capi/capiutil.c unsigned layer; layer 235 drivers/isdn/capi/capiutil.c for (cmsg->p++, layer = 1; layer;) { layer 240 drivers/isdn/capi/capiutil.c layer++; layer 243 drivers/isdn/capi/capiutil.c layer--; layer 389 drivers/media/common/siano/smsdvb-main.c c->layer[i].segment_count = lr->number_of_segments; layer 393 drivers/media/common/siano/smsdvb-main.c c->layer[i].modulation = sms_to_modulation(lr->constellation); layer 477 drivers/media/common/siano/smsdvb-main.c c->layer[i].segment_count = lr->number_of_segments; layer 481 drivers/media/common/siano/smsdvb-main.c c->layer[i].modulation = sms_to_modulation(lr->constellation); layer 1027 drivers/media/dvb-core/dvb_frontend.c c->layer[i].fec = FEC_AUTO; layer 1028 drivers/media/dvb-core/dvb_frontend.c c->layer[i].modulation = QAM_AUTO; layer 1029 drivers/media/dvb-core/dvb_frontend.c c->layer[i].interleaving = 0; layer 1030 drivers/media/dvb-core/dvb_frontend.c c->layer[i].segment_count = 0; layer 1429 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[0].fec; layer 1432 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[0].modulation; layer 1435 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[0].segment_count; layer 1438 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[0].interleaving; layer 1441 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[1].fec; layer 1444 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[1].modulation; layer 1447 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[1].segment_count; layer 1450 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[1].interleaving; layer 1453 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[2].fec; layer 1456 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[2].modulation; layer 1459 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[2].segment_count; layer 1462 drivers/media/dvb-core/dvb_frontend.c tvp->u.data = c->layer[2].interleaving; layer 1618 drivers/media/dvb-core/dvb_frontend.c c->layer[i].fec = FEC_AUTO; layer 1619 drivers/media/dvb-core/dvb_frontend.c c->layer[i].modulation = QAM_AUTO; layer 1620 drivers/media/dvb-core/dvb_frontend.c c->layer[i].interleaving = 0; layer 1621 drivers/media/dvb-core/dvb_frontend.c c->layer[i].segment_count = 0; layer 1917 drivers/media/dvb-core/dvb_frontend.c c->layer[0].fec = data; layer 1920 drivers/media/dvb-core/dvb_frontend.c c->layer[0].modulation = data; layer 1923 drivers/media/dvb-core/dvb_frontend.c c->layer[0].segment_count = data; layer 1926 drivers/media/dvb-core/dvb_frontend.c c->layer[0].interleaving = data; layer 1929 drivers/media/dvb-core/dvb_frontend.c c->layer[1].fec = data; layer 1932 drivers/media/dvb-core/dvb_frontend.c c->layer[1].modulation = data; layer 1935 drivers/media/dvb-core/dvb_frontend.c c->layer[1].segment_count = data; layer 1938 drivers/media/dvb-core/dvb_frontend.c c->layer[1].interleaving = data; layer 1941 drivers/media/dvb-core/dvb_frontend.c c->layer[2].fec = data; layer 1944 drivers/media/dvb-core/dvb_frontend.c c->layer[2].modulation = data; layer 1947 drivers/media/dvb-core/dvb_frontend.c c->layer[2].segment_count = data; layer 1950 drivers/media/dvb-core/dvb_frontend.c c->layer[2].interleaving = data; layer 1247 drivers/media/dvb-frontends/dib0090.c if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > layer 1250 drivers/media/dvb-frontends/dib0090.c ((state->fe->dtv_property_cache.layer[0].modulation == layer 1253 drivers/media/dvb-frontends/dib0090.c layer[0].modulation == QAM_16))) layer 1255 drivers/media/dvb-frontends/dib0090.c ((state->fe->dtv_property_cache.layer[1].segment_count > layer 1258 drivers/media/dvb-frontends/dib0090.c ((state->fe->dtv_property_cache.layer[1].modulation == layer 1261 drivers/media/dvb-frontends/dib0090.c layer[1].modulation == QAM_16))) layer 1263 drivers/media/dvb-frontends/dib0090.c ((state->fe->dtv_property_cache.layer[2].segment_count > layer 1266 drivers/media/dvb-frontends/dib0090.c ((state->fe->dtv_property_cache.layer[2].modulation == layer 1269 drivers/media/dvb-frontends/dib0090.c layer[2].modulation == QAM_16))) layer 1998 drivers/media/dvb-frontends/dib8000.c switch (c->layer[layer_index].modulation) { layer 2014 drivers/media/dvb-frontends/dib8000.c switch (c->layer[layer_index].fec) { layer 2033 drivers/media/dvb-frontends/dib8000.c time_intlv = fls(c->layer[layer_index].interleaving); layer 2037 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv); layer 2038 drivers/media/dvb-frontends/dib8000.c if (c->layer[layer_index].segment_count > 0) { layer 2042 drivers/media/dvb-frontends/dib8000.c if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64) layer 2043 drivers/media/dvb-frontends/dib8000.c max_constellation = c->layer[layer_index].modulation; layer 2046 drivers/media/dvb-frontends/dib8000.c if (c->layer[layer_index].modulation == QAM_64) layer 2047 drivers/media/dvb-frontends/dib8000.c max_constellation = c->layer[layer_index].modulation; layer 2203 drivers/media/dvb-frontends/dib8000.c if (c->layer[0].modulation == DQPSK) /* DQPSK */ layer 2208 drivers/media/dvb-frontends/dib8000.c if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ layer 2209 drivers/media/dvb-frontends/dib8000.c if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ layer 2214 drivers/media/dvb-frontends/dib8000.c if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ layer 2223 drivers/media/dvb-frontends/dib8000.c if (c->layer[0].modulation == DQPSK) /* DQPSK */ layer 2228 drivers/media/dvb-frontends/dib8000.c if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ layer 2229 drivers/media/dvb-frontends/dib8000.c if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ layer 2234 drivers/media/dvb-frontends/dib8000.c if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ layer 2245 drivers/media/dvb-frontends/dib8000.c if (c->layer[0].modulation == DQPSK) /* DQPSK */ layer 2250 drivers/media/dvb-frontends/dib8000.c if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ layer 2251 drivers/media/dvb-frontends/dib8000.c if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ layer 2256 drivers/media/dvb-frontends/dib8000.c if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */ layer 2368 drivers/media/dvb-frontends/dib8000.c state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0]; layer 2370 drivers/media/dvb-frontends/dib8000.c nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; layer 2375 drivers/media/dvb-frontends/dib8000.c nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; layer 2388 drivers/media/dvb-frontends/dib8000.c state->layer_b_nb_seg = c->layer[1].segment_count; layer 2389 drivers/media/dvb-frontends/dib8000.c state->layer_c_nb_seg = c->layer[2].segment_count; layer 2453 drivers/media/dvb-frontends/dib8000.c tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ; layer 2544 drivers/media/dvb-frontends/dib8000.c c->layer[0].modulation = QAM_64; layer 2545 drivers/media/dvb-frontends/dib8000.c c->layer[0].fec = FEC_2_3; layer 2546 drivers/media/dvb-frontends/dib8000.c c->layer[0].interleaving = 0; layer 2547 drivers/media/dvb-frontends/dib8000.c c->layer[0].segment_count = 13; layer 2580 drivers/media/dvb-frontends/dib8000.c c->layer[0].modulation = QAM_64; layer 2581 drivers/media/dvb-frontends/dib8000.c c->layer[0].fec = FEC_2_3; layer 2582 drivers/media/dvb-frontends/dib8000.c c->layer[0].interleaving = 0; layer 2583 drivers/media/dvb-frontends/dib8000.c c->layer[0].segment_count = 13; layer 2585 drivers/media/dvb-frontends/dib8000.c c->layer[0].segment_count = 13; layer 2967 drivers/media/dvb-frontends/dib8000.c if ((c->layer[i].segment_count > 13) || layer 2968 drivers/media/dvb-frontends/dib8000.c (c->layer[i].segment_count == 0)) { layer 2973 drivers/media/dvb-frontends/dib8000.c n_segs += c->layer[i].segment_count; layer 2975 drivers/media/dvb-frontends/dib8000.c if ((c->layer[i].modulation == QAM_AUTO) || layer 2976 drivers/media/dvb-frontends/dib8000.c (c->layer[i].fec == FEC_AUTO)) { layer 3239 drivers/media/dvb-frontends/dib8000.c if (c->layer[i].interleaving >= deeper_interleaver) { layer 3240 drivers/media/dvb-frontends/dib8000.c dprintk("layer%i: time interleaver = %d\n", i, c->layer[i].interleaving); layer 3241 drivers/media/dvb-frontends/dib8000.c if (c->layer[i].segment_count > 0) { /* valid layer */ layer 3242 drivers/media/dvb-frontends/dib8000.c deeper_interleaver = c->layer[0].interleaving; layer 3271 drivers/media/dvb-frontends/dib8000.c c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", layer 3272 drivers/media/dvb-frontends/dib8000.c c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", layer 3273 drivers/media/dvb-frontends/dib8000.c c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); layer 3292 drivers/media/dvb-frontends/dib8000.c c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", layer 3293 drivers/media/dvb-frontends/dib8000.c c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", layer 3294 drivers/media/dvb-frontends/dib8000.c c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); layer 3423 drivers/media/dvb-frontends/dib8000.c state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count; layer 3424 drivers/media/dvb-frontends/dib8000.c state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving; layer 3425 drivers/media/dvb-frontends/dib8000.c state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec; layer 3426 drivers/media/dvb-frontends/dib8000.c state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation; layer 3484 drivers/media/dvb-frontends/dib8000.c c->layer[i].segment_count = val; layer 3493 drivers/media/dvb-frontends/dib8000.c i, c->layer[i].segment_count); layer 3499 drivers/media/dvb-frontends/dib8000.c c->layer[i].interleaving = val; layer 3502 drivers/media/dvb-frontends/dib8000.c i, c->layer[i].interleaving); layer 3507 drivers/media/dvb-frontends/dib8000.c c->layer[i].fec = FEC_1_2; layer 3512 drivers/media/dvb-frontends/dib8000.c c->layer[i].fec = FEC_2_3; layer 3517 drivers/media/dvb-frontends/dib8000.c c->layer[i].fec = FEC_3_4; layer 3522 drivers/media/dvb-frontends/dib8000.c c->layer[i].fec = FEC_5_6; layer 3527 drivers/media/dvb-frontends/dib8000.c c->layer[i].fec = FEC_7_8; layer 3536 drivers/media/dvb-frontends/dib8000.c c->layer[i].modulation = DQPSK; layer 3541 drivers/media/dvb-frontends/dib8000.c c->layer[i].modulation = QPSK; layer 3546 drivers/media/dvb-frontends/dib8000.c c->layer[i].modulation = QAM_16; layer 3552 drivers/media/dvb-frontends/dib8000.c c->layer[i].modulation = QAM_64; layer 3567 drivers/media/dvb-frontends/dib8000.c state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = c->layer[i].segment_count; layer 3568 drivers/media/dvb-frontends/dib8000.c state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = c->layer[i].interleaving; layer 3569 drivers/media/dvb-frontends/dib8000.c state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec; layer 3570 drivers/media/dvb-frontends/dib8000.c state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = c->layer[i].modulation; layer 3693 drivers/media/dvb-frontends/dib8000.c state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count; layer 3694 drivers/media/dvb-frontends/dib8000.c state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving; layer 3695 drivers/media/dvb-frontends/dib8000.c state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec; layer 3696 drivers/media/dvb-frontends/dib8000.c state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation; layer 3983 drivers/media/dvb-frontends/dib8000.c static u32 dib8000_get_time_us(struct dvb_frontend *fe, int layer) layer 3993 drivers/media/dvb-frontends/dib8000.c if (layer >= 0) { layer 3994 drivers/media/dvb-frontends/dib8000.c ini_layer = layer; layer 3995 drivers/media/dvb-frontends/dib8000.c end_layer = layer + 1; layer 4032 drivers/media/dvb-frontends/dib8000.c nsegs = c->layer[i].segment_count; layer 4036 drivers/media/dvb-frontends/dib8000.c switch (c->layer[i].modulation) { layer 4050 drivers/media/dvb-frontends/dib8000.c switch (c->layer[i].fec) { layer 4074 drivers/media/dvb-frontends/dib8000.c interleaving = c->layer[i].interleaving; layer 4197 drivers/media/dvb-frontends/dib8000.c unsigned nsegs = c->layer[i].segment_count; layer 377 drivers/media/dvb-frontends/mb86a20s.c unsigned layer) layer 386 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) layer 388 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); layer 409 drivers/media/dvb-frontends/mb86a20s.c unsigned layer) layer 419 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) layer 421 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); layer 444 drivers/media/dvb-frontends/mb86a20s.c unsigned layer) layer 457 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) layer 459 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); layer 470 drivers/media/dvb-frontends/mb86a20s.c unsigned layer) layer 481 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) layer 484 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); layer 542 drivers/media/dvb-frontends/mb86a20s.c static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer, layer 617 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, layer 621 drivers/media/dvb-frontends/mb86a20s.c state->estimated_rate[layer] = rate; layer 628 drivers/media/dvb-frontends/mb86a20s.c int layer, rc; layer 646 drivers/media/dvb-frontends/mb86a20s.c for (layer = 0; layer < NUM_LAYERS; layer++) { layer 648 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer); layer 650 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_segment_count(state, layer); layer 654 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].segment_count = rc; layer 656 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].segment_count = 0; layer 657 drivers/media/dvb-frontends/mb86a20s.c state->estimated_rate[layer] = 0; layer 660 drivers/media/dvb-frontends/mb86a20s.c c->isdbt_layer_enabled |= 1 << layer; layer 661 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_modulation(state, layer); layer 666 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].modulation = rc; layer 667 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_fec(state, layer); layer 672 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].fec = rc; layer 673 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_interleaving(state, layer); layer 678 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].interleaving = rc; layer 679 drivers/media/dvb-frontends/mb86a20s.c mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation, layer 680 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].fec, layer 682 drivers/media/dvb-frontends/mb86a20s.c c->layer[layer].segment_count); layer 801 drivers/media/dvb-frontends/mb86a20s.c unsigned layer, layer 809 drivers/media/dvb-frontends/mb86a20s.c if (layer >= NUM_LAYERS) layer 818 drivers/media/dvb-frontends/mb86a20s.c if (!(rc & (1 << layer))) { layer 821 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer); layer 826 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_readreg(state, 0x55 + layer * 3); layer 830 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_readreg(state, 0x56 + layer * 3); layer 834 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_readreg(state, 0x57 + layer * 3); layer 841 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, *error); layer 844 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); layer 851 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); layer 858 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); layer 868 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, *count); layer 878 drivers/media/dvb-frontends/mb86a20s.c if (state->estimated_rate[layer] layer 879 drivers/media/dvb-frontends/mb86a20s.c && state->estimated_rate[layer] != *count) { layer 882 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, state->estimated_rate[layer]); layer 888 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3); layer 892 drivers/media/dvb-frontends/mb86a20s.c state->estimated_rate[layer] >> 16); layer 895 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3); layer 899 drivers/media/dvb-frontends/mb86a20s.c state->estimated_rate[layer] >> 8); layer 902 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3); layer 906 drivers/media/dvb-frontends/mb86a20s.c state->estimated_rate[layer]); layer 924 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer)); layer 927 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x53, val | (1 << layer)); layer 934 drivers/media/dvb-frontends/mb86a20s.c unsigned layer, layer 943 drivers/media/dvb-frontends/mb86a20s.c if (layer >= NUM_LAYERS) layer 952 drivers/media/dvb-frontends/mb86a20s.c if (!(rc & (1 << layer))) { layer 955 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer); layer 960 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_readreg(state, 0x64 + layer * 3); layer 964 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_readreg(state, 0x65 + layer * 3); layer 968 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_readreg(state, 0x66 + layer * 3); layer 975 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, *error); layer 978 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); layer 985 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); layer 996 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, *count); layer 1005 drivers/media/dvb-frontends/mb86a20s.c if (!state->estimated_rate[layer]) layer 1008 drivers/media/dvb-frontends/mb86a20s.c collect_rate = state->estimated_rate[layer] / 204 / 8; layer 1016 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, collect_rate); layer 1022 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2); layer 1028 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2); layer 1053 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer)); layer 1056 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer)); layer 1062 drivers/media/dvb-frontends/mb86a20s.c unsigned layer, layer 1070 drivers/media/dvb-frontends/mb86a20s.c if (layer >= NUM_LAYERS) layer 1083 drivers/media/dvb-frontends/mb86a20s.c if (!(rc & (1 << layer))) { layer 1086 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer); layer 1091 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2); layer 1098 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2); layer 1106 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, *error); layer 1109 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); layer 1116 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); layer 1126 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, *count); layer 1135 drivers/media/dvb-frontends/mb86a20s.c if (!state->estimated_rate[layer]) layer 1138 drivers/media/dvb-frontends/mb86a20s.c collect_rate = state->estimated_rate[layer] / 204 / 8; layer 1147 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, collect_rate); layer 1158 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2); layer 1164 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2); layer 1200 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val | (1 << layer)); layer 1203 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer)); layer 1435 drivers/media/dvb-frontends/mb86a20s.c int rc, val, layer; layer 1457 drivers/media/dvb-frontends/mb86a20s.c for (layer = 0; layer < NUM_LAYERS; layer++) { layer 1458 drivers/media/dvb-frontends/mb86a20s.c if (!(c->isdbt_layer_enabled & (1 << layer))) { layer 1459 drivers/media/dvb-frontends/mb86a20s.c c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1463 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3); layer 1470 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3); layer 1477 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3); layer 1485 drivers/media/dvb-frontends/mb86a20s.c switch (c->layer[layer].modulation) { layer 1503 drivers/media/dvb-frontends/mb86a20s.c c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL; layer 1504 drivers/media/dvb-frontends/mb86a20s.c c->cnr.stat[1 + layer].svalue = cnr; layer 1508 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer); layer 1536 drivers/media/dvb-frontends/mb86a20s.c int layer; layer 1559 drivers/media/dvb-frontends/mb86a20s.c for (layer = 0; layer < NUM_LAYERS + 1; layer++) { layer 1560 drivers/media/dvb-frontends/mb86a20s.c c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1561 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1562 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1563 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1564 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1565 drivers/media/dvb-frontends/mb86a20s.c c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1566 drivers/media/dvb-frontends/mb86a20s.c c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1574 drivers/media/dvb-frontends/mb86a20s.c int rc = 0, layer; layer 1598 drivers/media/dvb-frontends/mb86a20s.c for (layer = 0; layer < NUM_LAYERS; layer++) { layer 1599 drivers/media/dvb-frontends/mb86a20s.c if (c->isdbt_layer_enabled & (1 << layer)) { layer 1604 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_pre_ber(fe, layer, layer 1607 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; layer 1608 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_error.stat[1 + layer].uvalue += bit_error; layer 1609 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; layer 1610 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_count.stat[1 + layer].uvalue += bit_count; layer 1616 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1617 drivers/media/dvb-frontends/mb86a20s.c c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1620 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, rc); layer 1622 drivers/media/dvb-frontends/mb86a20s.c if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) layer 1626 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_post_ber(fe, layer, layer 1629 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER; layer 1630 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_error.stat[1 + layer].uvalue += bit_error; layer 1631 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER; layer 1632 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_count.stat[1 + layer].uvalue += bit_count; layer 1638 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1639 drivers/media/dvb-frontends/mb86a20s.c c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1642 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, rc); layer 1644 drivers/media/dvb-frontends/mb86a20s.c if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) layer 1648 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_get_blk_error(fe, layer, layer 1652 drivers/media/dvb-frontends/mb86a20s.c c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER; layer 1653 drivers/media/dvb-frontends/mb86a20s.c c->block_error.stat[1 + layer].uvalue += block_error; layer 1654 drivers/media/dvb-frontends/mb86a20s.c c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER; layer 1655 drivers/media/dvb-frontends/mb86a20s.c c->block_count.stat[1 + layer].uvalue += block_count; layer 1661 drivers/media/dvb-frontends/mb86a20s.c c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1662 drivers/media/dvb-frontends/mb86a20s.c c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE; layer 1665 drivers/media/dvb-frontends/mb86a20s.c __func__, 'A' + layer, rc); layer 1668 drivers/media/dvb-frontends/mb86a20s.c if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE) layer 1672 drivers/media/dvb-frontends/mb86a20s.c t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue; layer 1673 drivers/media/dvb-frontends/mb86a20s.c t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue; layer 1676 drivers/media/dvb-frontends/mb86a20s.c t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue; layer 1677 drivers/media/dvb-frontends/mb86a20s.c t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue; layer 1680 drivers/media/dvb-frontends/mb86a20s.c t_block_error += c->block_error.stat[1 + layer].uvalue; layer 1681 drivers/media/dvb-frontends/mb86a20s.c t_block_count += c->block_count.stat[1 + layer].uvalue; layer 220 drivers/media/dvb-frontends/tc90522.c c->layer[0].fec = c->fec_inner; layer 221 drivers/media/dvb-frontends/tc90522.c c->layer[0].modulation = c->modulation; layer 222 drivers/media/dvb-frontends/tc90522.c c->layer[0].segment_count = val[3] & 0x3f; /* slots */ layer 226 drivers/media/dvb-frontends/tc90522.c c->layer[1].fec = fec_conv_sat[v]; layer 228 drivers/media/dvb-frontends/tc90522.c c->layer[1].segment_count = 0; layer 230 drivers/media/dvb-frontends/tc90522.c c->layer[1].segment_count = val[4] & 0x3f; /* slots */ layer 235 drivers/media/dvb-frontends/tc90522.c c->layer[1].modulation = QPSK; layer 362 drivers/media/dvb-frontends/tc90522.c c->layer[0].segment_count = 0; layer 365 drivers/media/dvb-frontends/tc90522.c c->layer[0].segment_count = v; layer 366 drivers/media/dvb-frontends/tc90522.c c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2]; layer 367 drivers/media/dvb-frontends/tc90522.c c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5]; layer 369 drivers/media/dvb-frontends/tc90522.c c->layer[0].interleaving = v; layer 375 drivers/media/dvb-frontends/tc90522.c c->layer[1].segment_count = 0; layer 378 drivers/media/dvb-frontends/tc90522.c c->layer[1].segment_count = v; layer 379 drivers/media/dvb-frontends/tc90522.c c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5]; layer 380 drivers/media/dvb-frontends/tc90522.c c->layer[1].modulation = mod_conv[(val[2] & 0x07)]; layer 381 drivers/media/dvb-frontends/tc90522.c c->layer[1].interleaving = (val[3] & 0x1c) >> 2; layer 387 drivers/media/dvb-frontends/tc90522.c c->layer[2].segment_count = 0; layer 390 drivers/media/dvb-frontends/tc90522.c c->layer[2].segment_count = v; layer 391 drivers/media/dvb-frontends/tc90522.c c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)]; layer 392 drivers/media/dvb-frontends/tc90522.c c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3]; layer 393 drivers/media/dvb-frontends/tc90522.c c->layer[2].interleaving = (val[5] & 0xe0) >> 5; layer 46 drivers/media/pci/ttpci/dvb_filter.c ai->layer = 0; // 0 for AC3 layer 229 drivers/media/pci/ttpci/dvb_filter.h int layer; layer 42 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer); layer 63 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer) layer 65 drivers/media/platform/davinci/vpbe_display.c if (layer->cur_frm == layer->next_frm) layer 68 drivers/media/platform/davinci/vpbe_display.c layer->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns(); layer 69 drivers/media/platform/davinci/vpbe_display.c vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE); layer 71 drivers/media/platform/davinci/vpbe_display.c layer->cur_frm = layer->next_frm; layer 75 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer) layer 81 drivers/media/platform/davinci/vpbe_display.c if (list_empty(&layer->dma_queue) || layer 82 drivers/media/platform/davinci/vpbe_display.c (layer->cur_frm != layer->next_frm)) { layer 92 drivers/media/platform/davinci/vpbe_display.c layer->next_frm = list_entry(layer->dma_queue.next, layer 95 drivers/media/platform/davinci/vpbe_display.c list_del(&layer->next_frm->list); layer 98 drivers/media/platform/davinci/vpbe_display.c layer->next_frm->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE; layer 99 drivers/media/platform/davinci/vpbe_display.c addr = vb2_dma_contig_plane_dma_addr(&layer->next_frm->vb.vb2_buf, 0); layer 101 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, layer 110 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer; layer 140 drivers/media/platform/davinci/vpbe_display.c layer = disp_dev->dev[i]; layer 142 drivers/media/platform/davinci/vpbe_display.c if (!vb2_start_streaming_called(&layer->buffer_queue)) layer 145 drivers/media/platform/davinci/vpbe_display.c if (layer->layer_first_int) { layer 146 drivers/media/platform/davinci/vpbe_display.c layer->layer_first_int = 0; layer 150 drivers/media/platform/davinci/vpbe_display.c if ((V4L2_FIELD_NONE == layer->pix_fmt.field) && layer 154 drivers/media/platform/davinci/vpbe_display.c vpbe_isr_even_field(disp_dev, layer); layer 155 drivers/media/platform/davinci/vpbe_display.c vpbe_isr_odd_field(disp_dev, layer); layer 159 drivers/media/platform/davinci/vpbe_display.c layer->field_id ^= 1; layer 169 drivers/media/platform/davinci/vpbe_display.c if (fid != layer->field_id) { layer 171 drivers/media/platform/davinci/vpbe_display.c layer->field_id = fid; layer 179 drivers/media/platform/davinci/vpbe_display.c vpbe_isr_even_field(disp_dev, layer); layer 181 drivers/media/platform/davinci/vpbe_display.c vpbe_isr_odd_field(disp_dev, layer); layer 197 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = vb2_get_drv_priv(q); layer 198 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 204 drivers/media/platform/davinci/vpbe_display.c vb2_set_plane_payload(vb, 0, layer->pix_fmt.sizeimage); layer 228 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = vb2_get_drv_priv(vq); layer 229 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 238 drivers/media/platform/davinci/vpbe_display.c return sizes[0] < layer->pix_fmt.sizeimage ? -EINVAL : 0; layer 241 drivers/media/platform/davinci/vpbe_display.c sizes[0] = layer->pix_fmt.sizeimage; layer 256 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = vb2_get_drv_priv(vb->vb2_queue); layer 257 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp = layer->disp_dev; layer 258 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 266 drivers/media/platform/davinci/vpbe_display.c list_add_tail(&buf->list, &layer->dma_queue); layer 272 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = vb2_get_drv_priv(vq); layer 273 drivers/media/platform/davinci/vpbe_display.c struct osd_state *osd_device = layer->disp_dev->osd_device; layer 276 drivers/media/platform/davinci/vpbe_display.c osd_device->ops.disable_layer(osd_device, layer->layer_info.id); layer 279 drivers/media/platform/davinci/vpbe_display.c layer->next_frm = layer->cur_frm = list_entry(layer->dma_queue.next, layer 282 drivers/media/platform/davinci/vpbe_display.c list_del(&layer->cur_frm->list); layer 284 drivers/media/platform/davinci/vpbe_display.c layer->cur_frm->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE; layer 286 drivers/media/platform/davinci/vpbe_display.c layer->field_id = 0; layer 289 drivers/media/platform/davinci/vpbe_display.c ret = vpbe_set_osd_display_params(layer->disp_dev, layer); layer 293 drivers/media/platform/davinci/vpbe_display.c vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, layer 295 drivers/media/platform/davinci/vpbe_display.c list_for_each_entry_safe(buf, tmp, &layer->dma_queue, list) { layer 308 drivers/media/platform/davinci/vpbe_display.c layer->layer_first_int = 1; layer 315 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = vb2_get_drv_priv(vq); layer 316 drivers/media/platform/davinci/vpbe_display.c struct osd_state *osd_device = layer->disp_dev->osd_device; layer 317 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp = layer->disp_dev; layer 323 drivers/media/platform/davinci/vpbe_display.c osd_device->ops.disable_layer(osd_device, layer->layer_info.id); layer 327 drivers/media/platform/davinci/vpbe_display.c if (layer->cur_frm == layer->next_frm) { layer 328 drivers/media/platform/davinci/vpbe_display.c vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, layer 331 drivers/media/platform/davinci/vpbe_display.c if (layer->cur_frm) layer 332 drivers/media/platform/davinci/vpbe_display.c vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, layer 334 drivers/media/platform/davinci/vpbe_display.c if (layer->next_frm) layer 335 drivers/media/platform/davinci/vpbe_display.c vb2_buffer_done(&layer->next_frm->vb.vb2_buf, layer 339 drivers/media/platform/davinci/vpbe_display.c while (!list_empty(&layer->dma_queue)) { layer 340 drivers/media/platform/davinci/vpbe_display.c layer->next_frm = list_entry(layer->dma_queue.next, layer 342 drivers/media/platform/davinci/vpbe_display.c list_del(&layer->next_frm->list); layer 343 drivers/media/platform/davinci/vpbe_display.c vb2_buffer_done(&layer->next_frm->vb.vb2_buf, layer 362 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer) layer 365 drivers/media/platform/davinci/vpbe_display.c thiswin = layer->device_id; layer 373 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer) layer 375 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 381 drivers/media/platform/davinci/vpbe_display.c addr = vb2_dma_contig_plane_dma_addr(&layer->cur_frm->vb.vb2_buf, 0); layer 384 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, layer 389 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, 0); layer 397 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.enable = 1; layer 400 drivers/media/platform/davinci/vpbe_display.c _vpbe_display_get_other_win_layer(disp_dev, layer); layer 416 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer, layer 419 drivers/media/platform/davinci/vpbe_display.c struct display_layer_info *layer_info = &layer->layer_info; layer 420 drivers/media/platform/davinci/vpbe_display.c struct v4l2_pix_format *pixfmt = &layer->pix_fmt; layer 421 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 523 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer, layer 526 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 629 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 630 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 644 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 645 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp_dev = layer->disp_dev; layer 647 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 653 drivers/media/platform/davinci/vpbe_display.c "VIDIOC_S_SELECTION, layer id = %d\n", layer->device_id); layer 667 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, cfg); layer 669 drivers/media/platform/davinci/vpbe_display.c vpbe_disp_calculate_scale_factor(disp_dev, layer, layer 672 drivers/media/platform/davinci/vpbe_display.c vpbe_disp_adj_position(disp_dev, layer, rect.top, layer 675 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, cfg); layer 684 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, layer 685 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.h_zoom, layer 686 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.v_zoom); layer 688 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.h_exp, layer 689 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.v_exp); layer 696 drivers/media/platform/davinci/vpbe_display.c if ((layer->layer_info.h_zoom != ZOOM_X1) || layer 697 drivers/media/platform/davinci/vpbe_display.c (layer->layer_info.v_zoom != ZOOM_X1) || layer 698 drivers/media/platform/davinci/vpbe_display.c (layer->layer_info.h_exp != H_EXP_OFF) || layer 699 drivers/media/platform/davinci/vpbe_display.c (layer->layer_info.v_exp != V_EXP_OFF)) layer 712 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 713 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 714 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 715 drivers/media/platform/davinci/vpbe_display.c struct osd_state *osd_device = layer->disp_dev->osd_device; layer 720 drivers/media/platform/davinci/vpbe_display.c layer->device_id); layer 728 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, cfg); layer 751 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 752 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 766 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 767 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 771 drivers/media/platform/davinci/vpbe_display.c layer->device_id); layer 779 drivers/media/platform/davinci/vpbe_display.c fmt->fmt.pix = layer->pix_fmt; layer 787 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 788 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 792 drivers/media/platform/davinci/vpbe_display.c layer->device_id); layer 810 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 811 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp_dev = layer->disp_dev; layer 813 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 820 drivers/media/platform/davinci/vpbe_display.c layer->device_id); layer 822 drivers/media/platform/davinci/vpbe_display.c if (vb2_is_busy(&layer->buffer_queue)) layer 837 drivers/media/platform/davinci/vpbe_display.c layer->pix_fmt = *pixfmt; layer 841 drivers/media/platform/davinci/vpbe_display.c otherlayer = _vpbe_display_get_other_win_layer(disp_dev, layer); layer 856 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, cfg); layer 873 drivers/media/platform/davinci/vpbe_display.c layer); layer 879 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, cfg); layer 888 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id, cfg); layer 896 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 897 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp_dev = layer->disp_dev; layer 898 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 922 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 923 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 928 drivers/media/platform/davinci/vpbe_display.c if (vb2_is_busy(&layer->buffer_queue)) layer 954 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 955 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 977 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 978 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 1004 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1005 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 1010 drivers/media/platform/davinci/vpbe_display.c if (vb2_is_busy(&layer->buffer_queue)) layer 1033 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1034 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 1053 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1054 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 1083 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1084 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 1089 drivers/media/platform/davinci/vpbe_display.c if (vb2_is_busy(&layer->buffer_queue)) layer 1116 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1117 drivers/media/platform/davinci/vpbe_display.c struct vpbe_device *vpbe_dev = layer->disp_dev->vpbe_dev; layer 1140 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1141 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp_dev = layer->disp_dev; layer 1157 drivers/media/platform/davinci/vpbe_display.c if (!layer->usrs) { layer 1158 drivers/media/platform/davinci/vpbe_display.c if (mutex_lock_interruptible(&layer->opslock)) layer 1162 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id); layer 1163 drivers/media/platform/davinci/vpbe_display.c mutex_unlock(&layer->opslock); layer 1173 drivers/media/platform/davinci/vpbe_display.c layer->usrs++; layer 1186 drivers/media/platform/davinci/vpbe_display.c struct vpbe_layer *layer = video_drvdata(file); layer 1187 drivers/media/platform/davinci/vpbe_display.c struct osd_layer_config *cfg = &layer->layer_info.config; layer 1188 drivers/media/platform/davinci/vpbe_display.c struct vpbe_display *disp_dev = layer->disp_dev; layer 1194 drivers/media/platform/davinci/vpbe_display.c mutex_lock(&layer->opslock); layer 1197 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id); layer 1199 drivers/media/platform/davinci/vpbe_display.c layer->usrs--; layer 1201 drivers/media/platform/davinci/vpbe_display.c if (!layer->usrs) { layer 1205 drivers/media/platform/davinci/vpbe_display.c _vpbe_display_get_other_win_layer(disp_dev, layer); layer 1212 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id); layer 1214 drivers/media/platform/davinci/vpbe_display.c layer->layer_info.id); layer 1218 drivers/media/platform/davinci/vpbe_display.c mutex_unlock(&layer->opslock); layer 102 drivers/media/platform/davinci/vpbe_osd.c #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1)) layer 103 drivers/media/platform/davinci/vpbe_osd.c #define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1)) layer 409 drivers/media/platform/davinci/vpbe_osd.c static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer, layer 415 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 443 drivers/media/platform/davinci/vpbe_osd.c static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer) layer 445 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 463 drivers/media/platform/davinci/vpbe_osd.c static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer) layer 466 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 477 drivers/media/platform/davinci/vpbe_osd.c _osd_disable_layer(sd, layer); layer 488 drivers/media/platform/davinci/vpbe_osd.c static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer) layer 490 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 508 drivers/media/platform/davinci/vpbe_osd.c static int osd_enable_layer(struct osd_state *sd, enum osd_layer layer, layer 512 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 538 drivers/media/platform/davinci/vpbe_osd.c _osd_enable_layer(sd, layer); layer 557 drivers/media/platform/davinci/vpbe_osd.c static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer, layer 563 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 581 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 616 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &sd->win[layer]; layer 633 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 670 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 734 drivers/media/platform/davinci/vpbe_osd.c static void osd_start_layer(struct osd_state *sd, enum osd_layer layer, layer 739 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 746 drivers/media/platform/davinci/vpbe_osd.c _osd_start_layer(sd, layer, fb_base_phys, cbcr_ofst); layer 748 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_VID0) { layer 758 drivers/media/platform/davinci/vpbe_osd.c static void osd_get_layer_config(struct osd_state *sd, enum osd_layer layer, layer 762 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 784 drivers/media/platform/davinci/vpbe_osd.c static int try_layer_config(struct osd_state *sd, enum osd_layer layer, layer 788 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 799 drivers/media/platform/davinci/vpbe_osd.c bad_config = !is_vid_win(layer); layer 803 drivers/media/platform/davinci/vpbe_osd.c bad_config = !is_vid_win(layer); layer 807 drivers/media/platform/davinci/vpbe_osd.c bad_config = !is_vid_win(layer); layer 810 drivers/media/platform/davinci/vpbe_osd.c bad_config = !is_osd_win(layer); layer 816 drivers/media/platform/davinci/vpbe_osd.c bad_config = is_osd_win(layer); layer 819 drivers/media/platform/davinci/vpbe_osd.c bad_config = (layer != WIN_OSD1); layer 837 drivers/media/platform/davinci/vpbe_osd.c is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) { layer 840 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_OSD0) layer 856 drivers/media/platform/davinci/vpbe_osd.c if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) && layer 860 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_VID0) layer 912 drivers/media/platform/davinci/vpbe_osd.c enum osd_layer layer) layer 922 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_VID0) layer 925 drivers/media/platform/davinci/vpbe_osd.c else if (layer == WIN_VID1) layer 945 drivers/media/platform/davinci/vpbe_osd.c static void _osd_set_layer_config(struct osd_state *sd, enum osd_layer layer, layer 952 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 1220 drivers/media/platform/davinci/vpbe_osd.c static int osd_set_layer_config(struct osd_state *sd, enum osd_layer layer, layer 1224 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 1231 drivers/media/platform/davinci/vpbe_osd.c reject_config = try_layer_config(sd, layer, lconfig); layer 1245 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_OSD1) { layer 1251 drivers/media/platform/davinci/vpbe_osd.c _osd_disable_layer(sd, layer); layer 1255 drivers/media/platform/davinci/vpbe_osd.c _osd_set_layer_config(sd, layer, lconfig); layer 1257 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_OSD1) { layer 1305 drivers/media/platform/davinci/vpbe_osd.c ((layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1); layer 1348 drivers/media/platform/davinci/vpbe_osd.c if (layer == WIN_VID0) { layer 1360 drivers/media/platform/davinci/vpbe_osd.c static void osd_init_layer(struct osd_state *sd, enum osd_layer layer) layer 1363 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 1372 drivers/media/platform/davinci/vpbe_osd.c _osd_disable_layer(sd, layer); layer 1376 drivers/media/platform/davinci/vpbe_osd.c _osd_set_zoom(sd, layer, win->h_zoom, win->v_zoom); layer 1379 drivers/media/platform/davinci/vpbe_osd.c _osd_start_layer(sd, layer, win->fb_base_phys, 0); layer 1387 drivers/media/platform/davinci/vpbe_osd.c switch (layer) { layer 1390 drivers/media/platform/davinci/vpbe_osd.c osdwin = (layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1; layer 1398 drivers/media/platform/davinci/vpbe_osd.c _osd_set_layer_config(sd, layer, cfg); layer 1417 drivers/media/platform/davinci/vpbe_osd.c _osd_set_layer_config(sd, layer, cfg); layer 1424 drivers/media/platform/davinci/vpbe_osd.c static void osd_release_layer(struct osd_state *sd, enum osd_layer layer) layer 1427 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 1438 drivers/media/platform/davinci/vpbe_osd.c osd_init_layer(sd, layer); layer 1446 drivers/media/platform/davinci/vpbe_osd.c static int osd_request_layer(struct osd_state *sd, enum osd_layer layer) layer 1449 drivers/media/platform/davinci/vpbe_osd.c struct osd_window_state *win = &osd->win[layer]; layer 149 drivers/net/ethernet/intel/ice/ice_sched.c ice_sched_add_node(struct ice_port_info *pi, u8 layer, layer 183 drivers/net/ethernet/intel/ice/ice_sched.c if (hw->max_children[layer]) { layer 186 drivers/net/ethernet/intel/ice/ice_sched.c hw->max_children[layer], layer 196 drivers/net/ethernet/intel/ice/ice_sched.c node->tx_sched_layer = layer; layer 271 drivers/net/ethernet/intel/ice/ice_sched.c struct ice_sched_node *parent, u8 layer) layer 273 drivers/net/ethernet/intel/ice/ice_sched.c return pi->sib_head[parent->tc_num][layer]; layer 658 drivers/net/ethernet/intel/ice/ice_sched.c struct ice_sched_node *parent, u8 layer, u16 num_nodes, layer 705 drivers/net/ethernet/intel/ice/ice_sched.c status = ice_sched_add_node(pi, layer, &buf->generic[i]); layer 726 drivers/net/ethernet/intel/ice/ice_sched.c prev = ice_sched_get_first_node(pi, tc_node, layer); layer 734 drivers/net/ethernet/intel/ice/ice_sched.c if (!pi->sib_head[tc_node->tc_num][layer]) layer 735 drivers/net/ethernet/intel/ice/ice_sched.c pi->sib_head[tc_node->tc_num][layer] = new_node; layer 760 drivers/net/ethernet/intel/ice/ice_sched.c struct ice_sched_node *parent, u8 layer, layer 776 drivers/net/ethernet/intel/ice/ice_sched.c if (!parent || layer < hw->sw_entry_point_layer) layer 795 drivers/net/ethernet/intel/ice/ice_sched.c parent, layer, layer 822 drivers/net/ethernet/intel/ice/ice_sched.c layer, new_num_nodes, layer 829 drivers/net/ethernet/intel/ice/ice_sched.c status = ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, layer 861 drivers/net/ethernet/intel/ice/ice_sched.c u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; layer 863 drivers/net/ethernet/intel/ice/ice_sched.c if (layer > hw->sw_entry_point_layer) layer 864 drivers/net/ethernet/intel/ice/ice_sched.c return layer; layer 40 drivers/net/ethernet/intel/ice/ice_sched.h ice_sched_add_node(struct ice_port_info *pi, u8 layer, layer 261 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c field.layer = NIX_TXLAYER_OL3; layer 275 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c field.layer = NIX_TXLAYER_OL3; layer 290 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c field.layer = NIX_TXLAYER_OL4; layer 299 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c field.layer = NIX_TXLAYER_OL4; layer 869 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h u64 layer : 2; layer 873 drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h u64 layer : 2; layer 104 drivers/net/phy/dp83640.c int layer; layer 1342 drivers/net/phy/dp83640.c dp83640->layer = 0; layer 1349 drivers/net/phy/dp83640.c dp83640->layer = PTP_CLASS_L4; layer 1356 drivers/net/phy/dp83640.c dp83640->layer = PTP_CLASS_L4; layer 1363 drivers/net/phy/dp83640.c dp83640->layer = PTP_CLASS_L2; layer 1370 drivers/net/phy/dp83640.c dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; layer 1380 drivers/net/phy/dp83640.c if (dp83640->layer & PTP_CLASS_L2) { layer 1384 drivers/net/phy/dp83640.c if (dp83640->layer & PTP_CLASS_L4) { layer 1450 drivers/net/phy/dp83640.c if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) layer 478 drivers/parisc/pdc_stable.c static PATHS_ATTR(layer, 0644, pdcspath_layer_read, pdcspath_layer_write); layer 747 drivers/pci/pcie/aer.c int layer, agent; layer 756 drivers/pci/pcie/aer.c layer = AER_GET_LAYER_ERROR(info->severity, info->status); layer 761 drivers/pci/pcie/aer.c aer_error_layer[layer], aer_agent_string[agent]); layer 809 drivers/pci/pcie/aer.c int layer, agent, tlp_header_valid = 0; layer 822 drivers/pci/pcie/aer.c layer = AER_GET_LAYER_ERROR(aer_severity, status); layer 834 drivers/pci/pcie/aer.c aer_error_layer[layer], aer_agent_string[agent]); layer 738 drivers/s390/net/qeth_core.h enum qeth_discipline_id layer; layer 747 drivers/s390/net/qeth_core.h #define IS_LAYER2(card) ((card)->options.layer == QETH_DISCIPLINE_LAYER2) layer 748 drivers/s390/net/qeth_core.h #define IS_LAYER3(card) ((card)->options.layer == QETH_DISCIPLINE_LAYER3) layer 1302 drivers/s390/net/qeth_core_main.c card->options.layer = QETH_DISCIPLINE_UNDETERMINED; layer 5484 drivers/s390/net/qeth_core_main.c card->options.layer = discipline; layer 5494 drivers/s390/net/qeth_core_main.c card->options.layer = QETH_DISCIPLINE_UNDETERMINED; layer 376 drivers/s390/net/qeth_core_sys.c return sprintf(buf, "%i\n", card->options.layer); layer 410 drivers/s390/net/qeth_core_sys.c if (card->options.layer == newdis) layer 668 drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c .layer = PREVIEW_LAYER, layer 701 drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h u32 layer; layer 94 fs/overlayfs/export.c return oe->lowerstack[0].layer->idx; layer 115 fs/overlayfs/export.c origin_layer = OVL_E(dentry)->lowerstack[0].layer->idx; layer 330 fs/overlayfs/export.c oe->lowerstack->layer = lowerpath->layer; layer 355 fs/overlayfs/export.c if (oe->lowerstack[i].layer->idx == idx) layer 370 fs/overlayfs/export.c struct ovl_layer *layer) layer 387 fs/overlayfs/export.c if (ovl_dentry_real_at(connected, layer->idx) != parent) layer 405 fs/overlayfs/export.c } else if (ovl_dentry_real_at(this, layer->idx) != real) { layer 419 fs/overlayfs/export.c real, layer->idx, connected, err); layer 426 fs/overlayfs/export.c struct ovl_layer *layer); layer 433 fs/overlayfs/export.c struct ovl_layer *layer) layer 445 fs/overlayfs/export.c inode = ovl_lookup_inode(sb, real, !layer->idx); layer 457 fs/overlayfs/export.c if (!this && layer->idx && ofs->indexdir && !WARN_ON(!d_is_dir(real))) { layer 485 fs/overlayfs/export.c if (WARN_ON(ovl_dentry_real_at(this, layer->idx) != real)) { layer 499 fs/overlayfs/export.c struct ovl_layer *layer) layer 504 fs/overlayfs/export.c if (real == layer->mnt->mnt_root) layer 516 fs/overlayfs/export.c ancestor = ovl_lookup_real_inode(sb, next, layer); layer 520 fs/overlayfs/export.c if (parent == layer->mnt->mnt_root) { layer 552 fs/overlayfs/export.c struct ovl_layer *layer) layer 557 fs/overlayfs/export.c connected = ovl_lookup_real_ancestor(sb, real, layer); layer 565 fs/overlayfs/export.c layer->idx); layer 586 fs/overlayfs/export.c if (parent == layer->mnt->mnt_root) { layer 608 fs/overlayfs/export.c this = ovl_lookup_real_one(connected, next, layer); layer 624 fs/overlayfs/export.c layer); layer 644 fs/overlayfs/export.c real, layer->idx, connected, err); layer 659 fs/overlayfs/export.c struct ovl_layer *layer = upper ? &upper_layer : lowerpath->layer; layer 677 fs/overlayfs/export.c return ovl_lookup_real(sb, real, layer); layer 884 fs/overlayfs/inode.c int fsid = bylower ? lowerpath->layer->fsid : 0; layer 935 fs/overlayfs/inode.c fsid = lowerpath->layer->fsid; layer 359 fs/overlayfs/namei.c .layer = &ofs->lower_layers[i] layer 787 fs/overlayfs/namei.c path->mnt = oe->lowerstack[idx - 1].layer->mnt; layer 906 fs/overlayfs/namei.c d.last = lower.layer->idx == roe->numlower; layer 961 fs/overlayfs/namei.c stack[ctr].layer = lower.layer; layer 987 fs/overlayfs/namei.c i = lower.layer->idx - 1; layer 41 fs/overlayfs/ovl_entry.h struct ovl_layer *layer; layer 1477 fs/overlayfs/super.c oe->lowerstack[i].layer = &ofs->lower_layers[i]; layer 158 fs/overlayfs/util.c path->mnt = oe->lowerstack[0].layer->mnt; layer 170 fs/overlayfs/util.c path->mnt = oe->lowerstack[oe->numlower - 1].layer->mnt; layer 205 fs/overlayfs/util.c return oe->numlower ? oe->lowerstack[0].layer : NULL; layer 318 include/media/davinci/vpbe_osd.h int (*request_layer)(struct osd_state *sd, enum osd_layer layer); layer 319 include/media/davinci/vpbe_osd.h void (*release_layer)(struct osd_state *sd, enum osd_layer layer); layer 320 include/media/davinci/vpbe_osd.h int (*enable_layer)(struct osd_state *sd, enum osd_layer layer, layer 322 include/media/davinci/vpbe_osd.h void (*disable_layer)(struct osd_state *sd, enum osd_layer layer); layer 323 include/media/davinci/vpbe_osd.h int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer, layer 325 include/media/davinci/vpbe_osd.h void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer, layer 327 include/media/davinci/vpbe_osd.h void (*start_layer)(struct osd_state *sd, enum osd_layer layer, layer 339 include/media/davinci/vpbe_osd.h void (*set_zoom)(struct osd_state *sd, enum osd_layer layer, layer 621 include/media/dvb_frontend.h } layer[3]; layer 124 include/net/caif/caif_dev.h struct cflayer **layer, int (**rcv_func)( layer 43 include/net/caif/cfctrl.h void (*linksetup_rsp)(struct cflayer *layer, u8 linkid, layer 46 include/net/caif/cfctrl.h void (*linkdestroy_rsp)(struct cflayer *layer, u8 linkid); layer 53 include/net/caif/cfctrl.h void (*reject_rsp)(struct cflayer *layer, u8 linkid, layer 126 include/net/caif/cfctrl.h struct cfctrl_rsp *cfctrl_get_respfuncs(struct cflayer *layer); layer 16 include/net/caif/cfsrvl.h struct cflayer layer; layer 21 include/net/caif/cfsrvl.h void (*release)(struct cflayer *layer); layer 39 include/net/caif/cfsrvl.h bool cfsrvl_phyid_match(struct cflayer *layer, int phyid); layer 46 include/net/caif/cfsrvl.h u8 cfsrvl_getphyid(struct cflayer *layer); layer 50 include/net/caif/cfsrvl.h struct cfsrvl *s = container_of(layr, struct cfsrvl, layer); layer 59 include/net/caif/cfsrvl.h struct cfsrvl *s = container_of(layr, struct cfsrvl, layer); layer 462 include/net/pkt_cls.h static inline unsigned char * tcf_get_base_ptr(struct sk_buff *skb, int layer) layer 464 include/net/pkt_cls.h switch (layer) { layer 328 include/sound/wavefront.h struct wf_layer layer[WF_NUM_LAYERS]; layer 548 include/uapi/linux/cdrom.h struct dvd_layer layer[DVD_LAYERS]; layer 14 include/uapi/linux/tc_ematch/tc_em_cmp.h __u8 layer:4; layer 11 include/uapi/linux/tc_ematch/tc_em_nbyte.h __u8 layer:4; layer 34 net/caif/caif_dev.c struct cflayer layer; layer 159 net/caif/caif_dev.c caifd->layer.up-> layer 160 net/caif/caif_dev.c ctrlcmd(caifd->layer.up, layer 162 net/caif/caif_dev.c caifd->layer.id); layer 166 net/caif/caif_dev.c static int transmit(struct cflayer *layer, struct cfpkt *pkt) layer 170 net/caif/caif_dev.c container_of(layer, struct caif_device_entry, layer); layer 228 net/caif/caif_dev.c caifd->layer.up->ctrlcmd(caifd->layer.up, layer 230 net/caif/caif_dev.c caifd->layer.id); layer 257 net/caif/caif_dev.c if (!caifd || !caifd->layer.up || !caifd->layer.up->receive || layer 268 net/caif/caif_dev.c err = caifd->layer.up->receive(caifd->layer.up, pkt); layer 294 net/caif/caif_dev.c if (!caifd || !caifd->layer.up || !caifd->layer.up->ctrlcmd) { layer 302 net/caif/caif_dev.c caifd->layer.up->ctrlcmd(caifd->layer.up, layer 306 net/caif/caif_dev.c caifd->layer.id); layer 312 net/caif/caif_dev.c struct cflayer **layer, layer 326 net/caif/caif_dev.c *layer = &caifd->layer; layer 343 net/caif/caif_dev.c strlcpy(caifd->layer.name, dev->name, layer 344 net/caif/caif_dev.c sizeof(caifd->layer.name)); layer 345 net/caif/caif_dev.c caifd->layer.transmit = transmit; layer 348 net/caif/caif_dev.c &caifd->layer, layer 367 net/caif/caif_dev.c struct cflayer *layer, *link_support; layer 396 net/caif/caif_dev.c &layer, NULL); layer 410 net/caif/caif_dev.c cfcnfg_set_phy_state(cfg, &caifd->layer, true); layer 419 net/caif/caif_dev.c if (!caifd || !caifd->layer.up || !caifd->layer.up->ctrlcmd) { layer 424 net/caif/caif_dev.c cfcnfg_set_phy_state(cfg, &caifd->layer, false); layer 428 net/caif/caif_dev.c caifd->layer.up->ctrlcmd(caifd->layer.up, layer 430 net/caif/caif_dev.c caifd->layer.id); layer 475 net/caif/caif_dev.c cfcnfg_del_phy_layer(cfg, &caifd->layer) != 0) { layer 527 net/caif/caif_dev.c cfcnfg_set_phy_state(cfg, &caifd->layer, false); layer 531 net/caif/caif_dev.c cfcnfg_del_phy_layer(cfg, &caifd->layer) != 0)) { layer 48 net/caif/caif_socket.c struct cflayer layer; layer 116 net/caif/caif_socket.c if (cf_sk->layer.dn && cf_sk->layer.dn->modemcmd) layer 117 net/caif/caif_socket.c cf_sk->layer.dn->modemcmd(cf_sk->layer.dn, mode); layer 170 net/caif/caif_socket.c cf_sk = container_of(layr, struct caifsock, layer); layer 183 net/caif/caif_socket.c struct caifsock *cf_sk = container_of(layr, struct caifsock, layer); layer 189 net/caif/caif_socket.c struct caifsock *cf_sk = container_of(layr, struct caifsock, layer); layer 198 net/caif/caif_socket.c struct caifsock *cf_sk = container_of(layr, struct caifsock, layer); layer 214 net/caif/caif_socket.c caif_client_register_refcnt(&cf_sk->layer, layer 509 net/caif/caif_socket.c if (cf_sk->layer.dn == NULL) { layer 514 net/caif/caif_socket.c return cf_sk->layer.dn->transmit(cf_sk->layer.dn, pkt); layer 791 net/caif/caif_socket.c caif_disconnect_client(sock_net(sk), &cf_sk->layer); layer 792 net/caif/caif_socket.c caif_free_client(&cf_sk->layer); layer 830 net/caif/caif_socket.c cf_sk->layer.receive = caif_sktrecv_cb; layer 833 net/caif/caif_socket.c &cf_sk->layer, &ifindex, &headroom, &tailroom); layer 925 net/caif/caif_socket.c caif_disconnect_client(sock_net(sk), &cf_sk->layer); layer 1024 net/caif/caif_socket.c caif_free_client(&cf_sk->layer); layer 1093 net/caif/caif_socket.c cf_sk->layer.ctrlcmd = caif_ctrl_cb; layer 32 net/caif/caif_usb.c struct cflayer layer; layer 54 net/caif/caif_usb.c struct cfusbl *usbl = container_of(layr, struct cfusbl, layer); layer 92 net/caif/caif_usb.c caif_assert(offsetof(struct cfusbl, layer) == 0); layer 94 net/caif/caif_usb.c memset(&this->layer, 0, sizeof(this->layer)); layer 95 net/caif/caif_usb.c this->layer.receive = cfusbl_receive; layer 96 net/caif/caif_usb.c this->layer.transmit = cfusbl_transmit; layer 97 net/caif/caif_usb.c this->layer.ctrlcmd = cfusbl_ctrlcmd; layer 98 net/caif/caif_usb.c snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "usb%d", phyid); layer 99 net/caif/caif_usb.c this->layer.id = phyid; layer 127 net/caif/caif_usb.c struct cflayer *layer, *link_support; layer 173 net/caif/caif_usb.c &layer, &caif_usb_type.func); layer 178 net/caif/caif_usb.c strlcpy(layer->name, dev->name, sizeof(layer->name)); layer 24 net/caif/cfcnfg.c #define container_obj(layr) container_of(layr, struct cfcnfg, layer) layer 56 net/caif/cfcnfg.c struct cflayer layer; layer 63 net/caif/cfcnfg.c static void cfcnfg_linkup_rsp(struct cflayer *layer, u8 channel_id, layer 66 net/caif/cfcnfg.c static void cfcnfg_linkdestroy_rsp(struct cflayer *layer, u8 channel_id); layer 67 net/caif/cfcnfg.c static void cfcnfg_reject_rsp(struct cflayer *layer, u8 channel_id, layer 205 net/caif/cfcnfg.c static void cfcnfg_linkdestroy_rsp(struct cflayer *layer, u8 channel_id) layer 363 net/caif/cfcnfg.c static void cfcnfg_reject_rsp(struct cflayer *layer, u8 channel_id, layer 372 net/caif/cfcnfg.c cfcnfg_linkup_rsp(struct cflayer *layer, u8 channel_id, enum cfctrl_srv serv, layer 375 net/caif/cfcnfg.c struct cfcnfg *cnfg = container_obj(layer); layer 17 net/caif/cfctrl.c #define container_obj(layr) container_of(layr, struct cfctrl, serv.layer) layer 42 net/caif/cfctrl.c caif_assert(offsetof(struct cfctrl, serv.layer) == 0); layer 48 net/caif/cfctrl.c this->serv.layer.receive = cfctrl_recv; layer 49 net/caif/cfctrl.c sprintf(this->serv.layer.name, "ctrl"); layer 50 net/caif/cfctrl.c this->serv.layer.ctrlcmd = cfctrl_ctrlcmd; layer 57 net/caif/cfctrl.c return &this->serv.layer; layer 60 net/caif/cfctrl.c void cfctrl_remove(struct cflayer *layer) layer 63 net/caif/cfctrl.c struct cfctrl *ctrl = container_obj(layer); layer 71 net/caif/cfctrl.c kfree(layer); layer 163 net/caif/cfctrl.c struct cfctrl_rsp *cfctrl_get_respfuncs(struct cflayer *layer) layer 165 net/caif/cfctrl.c struct cfctrl *this = container_obj(layer); layer 172 net/caif/cfctrl.c info->channel_id = cfctrl->serv.layer.id; layer 176 net/caif/cfctrl.c void cfctrl_enum_req(struct cflayer *layer, u8 physlinkid) layer 179 net/caif/cfctrl.c struct cfctrl *cfctrl = container_obj(layer); layer 180 net/caif/cfctrl.c struct cflayer *dn = cfctrl->serv.layer.dn; layer 189 net/caif/cfctrl.c caif_assert(offsetof(struct cfctrl, serv.layer) == 0); layer 199 net/caif/cfctrl.c int cfctrl_linkup_request(struct cflayer *layer, layer 203 net/caif/cfctrl.c struct cfctrl *cfctrl = container_obj(layer); layer 211 net/caif/cfctrl.c struct cflayer *dn = cfctrl->serv.layer.dn; layer 218 net/caif/cfctrl.c if (cfctrl_cancel_req(layer, user_layer) > 0) { layer 294 net/caif/cfctrl.c count = cfctrl_cancel_req(&cfctrl->serv.layer, layer 304 net/caif/cfctrl.c int cfctrl_linkdown_req(struct cflayer *layer, u8 channelid, layer 309 net/caif/cfctrl.c struct cfctrl *cfctrl = container_obj(layer); layer 310 net/caif/cfctrl.c struct cflayer *dn = cfctrl->serv.layer.dn; layer 350 net/caif/cfctrl.c static int cfctrl_recv(struct cflayer *layer, struct cfpkt *pkt) layer 358 net/caif/cfctrl.c struct cfctrl *cfctrl = container_obj(layer); layer 501 net/caif/cfctrl.c cfctrl->res.reject_rsp(cfctrl->serv.layer.up, layer 507 net/caif/cfctrl.c layer.up, linkid, layer 520 net/caif/cfctrl.c cfctrl->res.linkdestroy_rsp(cfctrl->serv.layer.up, linkid); layer 25 net/caif/cfdbgl.c caif_assert(offsetof(struct cfsrvl, layer) == 0); layer 27 net/caif/cfdbgl.c dbg->layer.receive = cfdbgl_receive; layer 28 net/caif/cfdbgl.c dbg->layer.transmit = cfdbgl_transmit; layer 29 net/caif/cfdbgl.c snprintf(dbg->layer.name, CAIF_LAYER_NAME_SZ, "dbg%d", channel_id); layer 30 net/caif/cfdbgl.c return &dbg->layer; layer 51 net/caif/cfdbgl.c info->channel_id = service->layer.id; layer 32 net/caif/cfdgml.c caif_assert(offsetof(struct cfsrvl, layer) == 0); layer 34 net/caif/cfdgml.c dgm->layer.receive = cfdgml_receive; layer 35 net/caif/cfdgml.c dgm->layer.transmit = cfdgml_transmit; layer 36 net/caif/cfdgml.c snprintf(dgm->layer.name, CAIF_LAYER_NAME_SZ, "dgm%d", channel_id); layer 37 net/caif/cfdgml.c return &dgm->layer; layer 106 net/caif/cfdgml.c info->channel_id = service->layer.id; layer 20 net/caif/cffrml.c #define container_obj(layr) container_of(layr, struct cffrml, layer) layer 23 net/caif/cffrml.c struct cflayer layer; layer 46 net/caif/cffrml.c caif_assert(offsetof(struct cffrml, layer) == 0); layer 48 net/caif/cffrml.c this->layer.receive = cffrml_receive; layer 49 net/caif/cffrml.c this->layer.transmit = cffrml_transmit; layer 50 net/caif/cffrml.c this->layer.ctrlcmd = cffrml_ctrlcmd; layer 51 net/caif/cffrml.c snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "frm%d", phyid); layer 53 net/caif/cffrml.c this->layer.id = phyid; layer 57 net/caif/cffrml.c void cffrml_free(struct cflayer *layer) layer 59 net/caif/cffrml.c struct cffrml *this = container_obj(layer); layer 61 net/caif/cffrml.c kfree(layer); layer 18 net/caif/cfmuxl.c #define container_obj(layr) container_of(layr, struct cfmuxl, layer) layer 25 net/caif/cfmuxl.c struct cflayer layer; layer 54 net/caif/cfmuxl.c this->layer.receive = cfmuxl_receive; layer 55 net/caif/cfmuxl.c this->layer.transmit = cfmuxl_transmit; layer 56 net/caif/cfmuxl.c this->layer.ctrlcmd = cfmuxl_ctrlcmd; layer 61 net/caif/cfmuxl.c snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "mux"); layer 62 net/caif/cfmuxl.c return &this->layer; layer 250 net/caif/cfmuxl.c struct cflayer *layer; layer 253 net/caif/cfmuxl.c list_for_each_entry_rcu(layer, &muxl->srvl_list, node) { layer 255 net/caif/cfmuxl.c if (cfsrvl_phyid_match(layer, phyid) && layer->ctrlcmd) { layer 259 net/caif/cfmuxl.c layer->id != 0) layer 260 net/caif/cfmuxl.c cfmuxl_remove_uplayer(layr, layer->id); layer 263 net/caif/cfmuxl.c layer->ctrlcmd(layer, ctrl, phyid); layer 17 net/caif/cfrfml.c #define container_obj(layr) container_of(layr, struct cfrfml, serv.layer) layer 34 net/caif/cfrfml.c static void cfrfml_release(struct cflayer *layer) layer 36 net/caif/cfrfml.c struct cfsrvl *srvl = container_of(layer, struct cfsrvl, layer); layer 37 net/caif/cfrfml.c struct cfrfml *rfml = container_obj(&srvl->layer); layer 56 net/caif/cfrfml.c this->serv.layer.receive = cfrfml_receive; layer 57 net/caif/cfrfml.c this->serv.layer.transmit = cfrfml_transmit; layer 65 net/caif/cfrfml.c snprintf(this->serv.layer.name, CAIF_LAYER_NAME_SZ, layer 68 net/caif/cfrfml.c return &this->serv.layer; layer 167 net/caif/cfrfml.c err = rfml->serv.layer.up->receive(rfml->serv.layer.up, pkt); layer 201 net/caif/cfrfml.c cfpkt_info(pkt)->channel_id = rfml->serv.layer.id; layer 210 net/caif/cfrfml.c return rfml->serv.layer.dn->transmit(rfml->serv.layer.dn, pkt); layer 22 net/caif/cfserl.c struct cflayer layer; layer 39 net/caif/cfserl.c caif_assert(offsetof(struct cfserl, layer) == 0); layer 40 net/caif/cfserl.c this->layer.receive = cfserl_receive; layer 41 net/caif/cfserl.c this->layer.transmit = cfserl_transmit; layer 42 net/caif/cfserl.c this->layer.ctrlcmd = cfserl_ctrlcmd; layer 45 net/caif/cfserl.c snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "ser1"); layer 46 net/caif/cfserl.c return &this->layer; layer 153 net/caif/cfserl.c ret = layr->layer.up->receive(layr->layer.up, pkt); layer 175 net/caif/cfserl.c static int cfserl_transmit(struct cflayer *layer, struct cfpkt *newpkt) layer 177 net/caif/cfserl.c struct cfserl *layr = container_obj(layer); layer 181 net/caif/cfserl.c return layer->dn->transmit(layer->dn, newpkt); layer 26 net/caif/cfsrvl.c #define container_obj(layr) container_of(layr, struct cfsrvl, layer) layer 122 net/caif/cfsrvl.c info->channel_id = service->layer.id; layer 143 net/caif/cfsrvl.c info->channel_id = service->layer.id; layer 155 net/caif/cfsrvl.c static void cfsrvl_release(struct cflayer *layer) layer 157 net/caif/cfsrvl.c struct cfsrvl *service = container_of(layer, struct cfsrvl, layer); layer 166 net/caif/cfsrvl.c caif_assert(offsetof(struct cfsrvl, layer) == 0); layer 170 net/caif/cfsrvl.c service->layer.id = channel_id; layer 171 net/caif/cfsrvl.c service->layer.ctrlcmd = cfservl_ctrlcmd; layer 172 net/caif/cfsrvl.c service->layer.modemcmd = cfservl_modemcmd; layer 187 net/caif/cfsrvl.c u8 cfsrvl_getphyid(struct cflayer *layer) layer 189 net/caif/cfsrvl.c struct cfsrvl *servl = container_obj(layer); layer 193 net/caif/cfsrvl.c bool cfsrvl_phyid_match(struct cflayer *layer, int phyid) layer 195 net/caif/cfsrvl.c struct cfsrvl *servl = container_obj(layer); layer 205 net/caif/cfsrvl.c servl->release(&servl->layer); layer 217 net/caif/cfsrvl.c service = container_of(adapt_layer->dn, struct cfsrvl, layer); layer 32 net/caif/cfutill.c caif_assert(offsetof(struct cfsrvl, layer) == 0); layer 34 net/caif/cfutill.c util->layer.receive = cfutill_receive; layer 35 net/caif/cfutill.c util->layer.transmit = cfutill_transmit; layer 36 net/caif/cfutill.c snprintf(util->layer.name, CAIF_LAYER_NAME_SZ, "util1"); layer 37 net/caif/cfutill.c return &util->layer; layer 96 net/caif/cfutill.c info->channel_id = service->layer.id; layer 21 net/caif/cfveil.c #define container_obj(layr) container_of(layr, struct cfsrvl, layer) layer 31 net/caif/cfveil.c caif_assert(offsetof(struct cfsrvl, layer) == 0); layer 33 net/caif/cfveil.c vei->layer.receive = cfvei_receive; layer 34 net/caif/cfveil.c vei->layer.transmit = cfvei_transmit; layer 35 net/caif/cfveil.c snprintf(vei->layer.name, CAIF_LAYER_NAME_SZ, "vei%d", channel_id); layer 36 net/caif/cfveil.c return &vei->layer; layer 94 net/caif/cfveil.c info->channel_id = service->layer.id; layer 27 net/caif/cfvidl.c caif_assert(offsetof(struct cfsrvl, layer) == 0); layer 30 net/caif/cfvidl.c vid->layer.receive = cfvidl_receive; layer 31 net/caif/cfvidl.c vid->layer.transmit = cfvidl_transmit; layer 32 net/caif/cfvidl.c snprintf(vid->layer.name, CAIF_LAYER_NAME_SZ, "vid1"); layer 33 net/caif/cfvidl.c return &vid->layer; layer 62 net/caif/cfvidl.c info->channel_id = service->layer.id; layer 25 net/sched/em_cmp.c unsigned char *ptr = tcf_get_base_ptr(skb, cmp->layer) + cmp->off; layer 43 net/sched/em_nbyte.c unsigned char *ptr = tcf_get_base_ptr(skb, nbyte->hdr.layer); layer 750 sound/isa/wavefront/wavefront_synth.c if (prog.layer[l].mute) { layer 752 sound/isa/wavefront/wavefront_synth.c [prog.layer[l].patch_number] |= layer 822 sound/isa/wavefront/wavefront_synth.c if (header->hdr.pr.layer[i].mute) { layer 823 sound/isa/wavefront/wavefront_synth.c dev->patch_status[header->hdr.pr.layer[i].patch_number] |=