lane_width       5164 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 lane_width;
lane_width       5233 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		lane_width = amdgpu_get_pcie_lanes(adev);
lane_width       5234 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
lane_width       6376 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	u32 lane_width;
lane_width       6384 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		lane_width = amdgpu_get_pcie_lanes(adev);
lane_width       6385 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
lane_width         97 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h 	uint8_t lane_width;
lane_width        537 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth);
lane_width        577 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth);
lane_width        569 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 							pcie_table->entries[i].lane_width));
lane_width       1268 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 							bios_pcie_table->entries[i].lane_width);
lane_width        843 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		pcie_table->entries[i].lane_width =
lane_width       3267 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
lane_width       3364 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				lane_width = data->pcie_width_level1;
lane_width       3367 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				lane_width = pptable->PcieLaneCount[i];
lane_width       3374 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(lane_width == 1) ? "x1" :
lane_width       3375 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(lane_width == 2) ? "x2" :
lane_width       3376 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(lane_width == 3) ? "x4" :
lane_width       3377 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(lane_width == 4) ? "x8" :
lane_width       3378 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(lane_width == 5) ? "x12" :
lane_width       3379 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(lane_width == 6) ? "x16" : "",
lane_width       3382 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					(current_lane_width == lane_width) ?
lane_width        945 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	uint32_t gen_speed, lane_width;
lane_width       1063 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
lane_width       1080 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 					(lane_width == pptable->PcieLaneCount[i]) ?
lane_width       4702 drivers/gpu/drm/radeon/si_dpm.c 	u32 lane_width;
lane_width       4771 drivers/gpu/drm/radeon/si_dpm.c 		lane_width = radeon_get_pcie_lanes(rdev);
lane_width       4772 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
lane_width       5918 drivers/gpu/drm/radeon/si_dpm.c 	u32 lane_width;
lane_width       5926 drivers/gpu/drm/radeon/si_dpm.c 		lane_width = radeon_get_pcie_lanes(rdev);
lane_width       5927 drivers/gpu/drm/radeon/si_dpm.c 		si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);